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Commit c9cf4a01 authored by Cyrill Gorcunov's avatar Cyrill Gorcunov Committed by Ingo Molnar
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perf, x86, Pentium4: Add RAW events verification 



Implements verification of

- Bits of ESCR EventMask field (meaningful bits in field are hardware
  predefined and others bits should be set to zero)

- INSTR_COMPLETED event (it is available on predefined cpu model only)

- Thread shared events (they should be guarded by "perf_event_paranoid"
  sysctl due to security reason). The side effect of this action is
  that PERF_COUNT_HW_BUS_CYCLES become a "paranoid" general event.

Signed-off-by: default avatarCyrill Gorcunov <gorcunov@openvz.org>
Tested-by: default avatarLin Ming <ming.m.lin@intel.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Peter Zijlstra <peterz@infradead.org>
LKML-Reference: <20100825182334.GB14874@lenovo>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 14416c35

arch/x86/include/asm/perf_event_p4.h

+22 −30
Original line number Diff line number Diff line
@@ -36,19 +36,6 @@ 
#define P4_ESCR_EMASK(v)	((v) << P4_ESCR_EVENTMASK_SHIFT)

#define P4_ESCR_TAG(v)		((v) << P4_ESCR_TAG_SHIFT)



/* Non HT mask */

#define P4_ESCR_MASK			\

	(P4_ESCR_EVENT_MASK	|	\

	P4_ESCR_EVENTMASK_MASK	|	\

	P4_ESCR_TAG_MASK	|	\

	P4_ESCR_TAG_ENABLE	|	\

	P4_ESCR_T0_OS		|	\

	P4_ESCR_T0_USR)



/* HT mask */

#define P4_ESCR_MASK_HT			\

	(P4_ESCR_MASK |	P4_ESCR_T1_OS | P4_ESCR_T1_USR)



#define P4_CCCR_OVF			0x80000000U

#define P4_CCCR_CASCADE			0x40000000U

#define P4_CCCR_OVF_PMI_T0		0x04000000U
@@ -70,23 +57,6 @@ 
#define P4_CCCR_THRESHOLD(v)		((v) << P4_CCCR_THRESHOLD_SHIFT)

#define P4_CCCR_ESEL(v)			((v) << P4_CCCR_ESCR_SELECT_SHIFT)



/* Non HT mask */

#define P4_CCCR_MASK				\

	(P4_CCCR_OVF			|	\

	P4_CCCR_CASCADE			|	\

	P4_CCCR_OVF_PMI_T0		|	\

	P4_CCCR_FORCE_OVF		|	\

	P4_CCCR_EDGE			|	\

	P4_CCCR_THRESHOLD_MASK		|	\

	P4_CCCR_COMPLEMENT		|	\

	P4_CCCR_COMPARE			|	\

	P4_CCCR_ESCR_SELECT_MASK	|	\

	P4_CCCR_ENABLE)



/* HT mask */

#define P4_CCCR_MASK_HT				\

	(P4_CCCR_MASK | P4_CCCR_OVF_PMI_T1 | P4_CCCR_THREAD_ANY)



#define P4_GEN_ESCR_EMASK(class, name, bit)	\

	class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT)

#define P4_ESCR_EMASK_BIT(class, name)		class##__##name
@@ -127,6 +97,28 @@ 
#define P4_CONFIG_HT_SHIFT		63

#define P4_CONFIG_HT			(1ULL << P4_CONFIG_HT_SHIFT)



/*

 * The bits we allow to pass for RAW events

 */

#define P4_CONFIG_MASK_ESCR		\

	P4_ESCR_EVENT_MASK	|	\

	P4_ESCR_EVENTMASK_MASK	|	\

	P4_ESCR_TAG_MASK	|	\

	P4_ESCR_TAG_ENABLE



#define P4_CONFIG_MASK_CCCR		\

	P4_CCCR_EDGE		|	\

	P4_CCCR_THRESHOLD_MASK	|	\

	P4_CCCR_COMPLEMENT	|	\

	P4_CCCR_COMPARE		|	\

	P4_CCCR_THREAD_ANY	|	\

	P4_CCCR_RESERVED



/* some dangerous bits are reserved for kernel internals */

#define P4_CONFIG_MASK				  	  \

	(p4_config_pack_escr(P4_CONFIG_MASK_ESCR))	| \

	(p4_config_pack_cccr(P4_CONFIG_MASK_CCCR))



static inline bool p4_is_event_cascaded(u64 config)

{

	u32 cccr = p4_config_unpack_cccr(config);

arch/x86/kernel/cpu/perf_event_p4.c

+268 −24

File changed.

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