Merge master.kernel.org:/home/rmk/linux-2.6-arm (b54a063d) · Commits · e / devices / android_kernel_samsung_smdk4412

Documentation/arm/README

+3 −4

Original line number	Original line	Diff line number	Diff line
	@@ -8,10 +8,9 @@ Compilation of kernel
	---------------------		---------------------

	In order to compile ARM Linux, you will need a compiler capable of		In order to compile ARM Linux, you will need a compiler capable of
	generating ARM ELF code with GNU extensions. GCC 2.95.1, EGCS		generating ARM ELF code with GNU extensions. GCC 3.3 is known to be
	1.1.2, and GCC 3.3 are known to be good compilers. Fortunately, you		a good compiler. Fortunately, you needn't guess. The kernel will report
	needn't guess. The kernel will report an error if your compiler is		an error if your compiler is a recognized offender.
	a recognized offender.

	To build ARM Linux natively, you shouldn't have to alter the ARCH = line		To build ARM Linux natively, you shouldn't have to alter the ARCH = line
	in the top level Makefile. However, if you don't have the ARM Linux ELF		in the top level Makefile. However, if you don't have the ARM Linux ELF

MAINTAINERS

+5 −0

Original line number	Original line	Diff line number	Diff line
	@@ -297,6 +297,11 @@ P: Richard Purdie
	M: rpurdie@rpsys.net		M: rpurdie@rpsys.net
	S: Maintained		S: Maintained

			ARM/TOSA MACHINE SUPPORT
			P: Dirk Opfer
			M: dirk@opfer-online.de
			S: Maintained

	ARM/PLEB SUPPORT		ARM/PLEB SUPPORT
	P: Peter Chubb		P: Peter Chubb
	M: pleb@gelato.unsw.edu.au		M: pleb@gelato.unsw.edu.au

arch/arm/kernel/entry-armv.S

+7 −8

Original line number	Original line	Diff line number	Diff line
	@@ -785,7 +785,7 @@ __kuser_helper_end:
	* SP points to a minimal amount of processor-private memory, the address		* SP points to a minimal amount of processor-private memory, the address
	* of which is copied into r0 for the mode specific abort handler.		* of which is copied into r0 for the mode specific abort handler.
	*/		*/
	.macro vector_stub, name, correction=0		.macro vector_stub, name, mode, correction=0
	.align 5		.align 5

	vector_\name:		vector_\name:
	@@ -805,15 +805,14 @@ vector_\name:
	@ Prepare for SVC32 mode. IRQs remain disabled.		@ Prepare for SVC32 mode. IRQs remain disabled.
	@		@
	mrs r0, cpsr		mrs r0, cpsr
	bic r0, r0, #MODE_MASK		eor r0, r0, #(\mode ^ SVC_MODE)
	orr r0, r0, #SVC_MODE
	msr spsr_cxsf, r0		msr spsr_cxsf, r0

	@		@
	@ the branch table must immediately follow this code		@ the branch table must immediately follow this code
	@		@
	mov r0, sp
	and lr, lr, #0x0f		and lr, lr, #0x0f
			mov r0, sp
	ldr lr, [pc, lr, lsl #2]		ldr lr, [pc, lr, lsl #2]
	movs pc, lr @ branch to handler in SVC mode		movs pc, lr @ branch to handler in SVC mode
	.endm		.endm
	@@ -823,7 +822,7 @@ __stubs_start:
	/*		/*
	* Interrupt dispatcher		* Interrupt dispatcher
	*/		*/
	vector_stub irq, 4		vector_stub irq, IRQ_MODE, 4

	.long __irq_usr @ 0 (USR_26 / USR_32)		.long __irq_usr @ 0 (USR_26 / USR_32)
	.long __irq_invalid @ 1 (FIQ_26 / FIQ_32)		.long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
	@@ -846,7 +845,7 @@ __stubs_start:
	* Data abort dispatcher		* Data abort dispatcher
	* Enter in ABT mode, spsr = USR CPSR, lr = USR PC		* Enter in ABT mode, spsr = USR CPSR, lr = USR PC
	*/		*/
	vector_stub dabt, 8		vector_stub dabt, ABT_MODE, 8

	.long __dabt_usr @ 0 (USR_26 / USR_32)		.long __dabt_usr @ 0 (USR_26 / USR_32)
	.long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)		.long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
	@@ -869,7 +868,7 @@ __stubs_start:
	* Prefetch abort dispatcher		* Prefetch abort dispatcher
	* Enter in ABT mode, spsr = USR CPSR, lr = USR PC		* Enter in ABT mode, spsr = USR CPSR, lr = USR PC
	*/		*/
	vector_stub pabt, 4		vector_stub pabt, ABT_MODE, 4

	.long __pabt_usr @ 0 (USR_26 / USR_32)		.long __pabt_usr @ 0 (USR_26 / USR_32)
	.long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)		.long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
	@@ -892,7 +891,7 @@ __stubs_start:
	* Undef instr entry dispatcher		* Undef instr entry dispatcher
	* Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC		* Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
	*/		*/
	vector_stub und		vector_stub und, UND_MODE

	.long __und_usr @ 0 (USR_26 / USR_32)		.long __und_usr @ 0 (USR_26 / USR_32)
	.long __und_invalid @ 1 (FIQ_26 / FIQ_32)		.long __und_invalid @ 1 (FIQ_26 / FIQ_32)

arch/arm/kernel/setup.c

+8 −2

Original line number	Original line	Diff line number	Diff line
	@@ -338,6 +338,7 @@ void cpu_init(void)
	BUG();		BUG();
	}		}

			if (system_state == SYSTEM_BOOTING)
	dump_cpu_info(cpu);		dump_cpu_info(cpu);

	/*		/*
	@@ -838,7 +839,12 @@ static int c_show(struct seq_file m, void v)

	#if defined(CONFIG_SMP)		#if defined(CONFIG_SMP)
	for_each_online_cpu(i) {		for_each_online_cpu(i) {
	seq_printf(m, "Processor\t: %d\n", i);		/*
			* glibc reads /proc/cpuinfo to determine the number of
			* online processors, looking for lines beginning with
			* "processor". Give glibc what it expects.
			*/
			seq_printf(m, "processor\t: %d\n", i);
	seq_printf(m, "BogoMIPS\t: %lu.%02lu\n\n",		seq_printf(m, "BogoMIPS\t: %lu.%02lu\n\n",
	per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ),		per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ),
	(per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100);		(per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100);

arch/arm/mach-ixp2000/uengine.c

+5 −6

Original line number	Original line	Diff line number	Diff line
	@@ -91,8 +91,8 @@ EXPORT_SYMBOL(ixp2000_uengine_csr_write);

	void ixp2000_uengine_reset(u32 uengine_mask)		void ixp2000_uengine_reset(u32 uengine_mask)
	{		{
	ixp2000_reg_write(IXP2000_RESET1, uengine_mask & ixp2000_uengine_mask);		ixp2000_reg_wrb(IXP2000_RESET1, uengine_mask & ixp2000_uengine_mask);
	ixp2000_reg_write(IXP2000_RESET1, 0);		ixp2000_reg_wrb(IXP2000_RESET1, 0);
	}		}
	EXPORT_SYMBOL(ixp2000_uengine_reset);		EXPORT_SYMBOL(ixp2000_uengine_reset);

	@@ -452,21 +452,20 @@ static int __init ixp2000_uengine_init(void)
	/*		/*
	* Reset microengines.		* Reset microengines.
	*/		*/
	ixp2000_reg_write(IXP2000_RESET1, ixp2000_uengine_mask);		ixp2000_uengine_reset(ixp2000_uengine_mask);
	ixp2000_reg_write(IXP2000_RESET1, 0);

	/*		/*
	* Synchronise timestamp counters across all microengines.		* Synchronise timestamp counters across all microengines.
	*/		*/
	value = ixp2000_reg_read(IXP2000_MISC_CONTROL);		value = ixp2000_reg_read(IXP2000_MISC_CONTROL);
	ixp2000_reg_write(IXP2000_MISC_CONTROL, value & ~0x80);		ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value & ~0x80);
	for (uengine = 0; uengine < 32; uengine++) {		for (uengine = 0; uengine < 32; uengine++) {
	if (ixp2000_uengine_mask & (1 << uengine)) {		if (ixp2000_uengine_mask & (1 << uengine)) {
	ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);		ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
	ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);		ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);
	}		}
	}		}
	ixp2000_reg_write(IXP2000_MISC_CONTROL, value \| 0x80);		ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value \| 0x80);

	return 0;		return 0;
	}		}