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Commit 76befb8c authored by Ben Skeggs's avatar Ben Skeggs
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drm/nv50: fix instmem binding on IGPs to point at stolen system memory 



This also modifies the unused PRAMIN PT entries to be all zeroes, can't
really recall why I used 9/0 initially, just that it didn't work for
some reason.  It was likely masking a bug elsewhere that's since been
fixed.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 531e7713

drivers/gpu/drm/nouveau/nouveau_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -583,6 +583,7 @@ struct drm_nouveau_private { 
	uint64_t vm_end;

	struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];

	int vm_vram_pt_nr;

	uint64_t vram_sys_base;



	/* the mtrr covering the FB */

	int fb_mtrr;

drivers/gpu/drm/nouveau/nv50_instmem.c

+40 −18
Original line number Diff line number Diff line
@@ -76,6 +76,11 @@ nv50_instmem_init(struct drm_device *dev) 
	for (i = 0x1700; i <= 0x1710; i += 4)

		priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i);



	if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac)

		dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10) << 12;

	else

		dev_priv->vram_sys_base = 0;



	/* Reserve the last MiB of VRAM, we should probably try to avoid

	 * setting up the below tables over the top of the VBIOS image at

	 * some point.
@@ -176,12 +181,24 @@ nv50_instmem_init(struct drm_device *dev) 
	if (ret)

		return ret;



	for (i = 0, v = c_offset; i < pt_size; i += 8, v += 0x1000) {

		if (v < (c_offset + c_size))

			BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v | 1);

		else

			BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000009);

	v = c_offset | 1;

	if (dev_priv->vram_sys_base) {

		v += dev_priv->vram_sys_base;

		v |= 0x30;

	}



	i = 0;

	while (v < dev_priv->vram_sys_base + c_offset + c_size) {

		BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v);

		BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);

		v += 0x1000;

		i += 8;

	}



	while (i < pt_size) {

		BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000000);

		BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);

		i += 8;

	}



	BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->instance | 0x63);
@@ -416,7 +433,9 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) 
{

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;

	uint32_t pte, pte_end, vram;

	struct nouveau_gpuobj *pramin_pt = priv->pramin_pt->gpuobj;

	uint32_t pte, pte_end;

	uint64_t vram;



	if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound)

		return -EINVAL;
@@ -424,20 +443,24 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) 
	NV_DEBUG(dev, "st=0x%0llx sz=0x%0llx\n",

		 gpuobj->im_pramin->start, gpuobj->im_pramin->size);



	pte     = (gpuobj->im_pramin->start >> 12) << 3;

	pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte;

	pte     = (gpuobj->im_pramin->start >> 12) << 1;

	pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;

	vram    = gpuobj->im_backing_start;



	NV_DEBUG(dev, "pramin=0x%llx, pte=%d, pte_end=%d\n",

		 gpuobj->im_pramin->start, pte, pte_end);

	NV_DEBUG(dev, "first vram page: 0x%08x\n", gpuobj->im_backing_start);



	vram |= 1;

	if (dev_priv->vram_sys_base) {

		vram += dev_priv->vram_sys_base;

		vram |= 0x30;

	}



	dev_priv->engine.instmem.prepare_access(dev, true);

	while (pte < pte_end) {

		nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 0)/4, vram | 1);

		nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000);



		pte += 8;

		nv_wo32(dev, pramin_pt, pte++, lower_32_bits(vram));

		nv_wo32(dev, pramin_pt, pte++, upper_32_bits(vram));

		vram += NV50_INSTMEM_PAGE_SIZE;

	}

	dev_priv->engine.instmem.finish_access(dev);
@@ -470,14 +493,13 @@ nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) 
	if (gpuobj->im_bound == 0)

		return -EINVAL;



	pte     = (gpuobj->im_pramin->start >> 12) << 3;

	pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte;

	pte     = (gpuobj->im_pramin->start >> 12) << 1;

	pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;



	dev_priv->engine.instmem.prepare_access(dev, true);

	while (pte < pte_end) {

		nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 0)/4, 0x00000009);

		nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000);

		pte += 8;

		nv_wo32(dev, priv->pramin_pt->gpuobj, pte++, 0x00000000);

		nv_wo32(dev, priv->pramin_pt->gpuobj, pte++, 0x00000000);

	}

	dev_priv->engine.instmem.finish_access(dev);