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Commit 528ba4ef authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] MIPS doesn't need compat_sys_getdents.
  [MIPS] JMR3927: Fixup another victim of the irq pt_regs cleanup.
  [MIPS] EMMA 2 / Markeins: struct resource takes physical addresses.
  [MIPS] EMMA 2 / Markeins: Convert to name struct resource initialization.
  [MIPS] EMMA 2 / Markeins: Formitting fixes split from actual address fixes.
  [MIPS] EMMA 2 / Markeins: Fix build wreckage due to genirq wreckage.
  [MIPS] Ocelot G: Fix build error and numerous warnings.
  [MIPS] Fix return value of TXX9 SPI interrupt handler
  [MIPS] Au1000: Fix warning about unused variable.
  [MIPS] Wire up getcpu(2) and epoll_wait(2) syscalls.
  [MIPS] Make SB1 cache flushes not to use on_each_cpu
  [MIPS] Fix warning about unused definition in c-sb1.c
  [MIPS] SMTC: Make 8 the default number of processors.
  [MIPS] Oprofile: Fix MIPSxx counter number detection.
  [MIPS] Au1xx0 code sets incorrect mips_hpt_frequency
  [MIPS] Oprofile: fix on non-VSMP / non-SMTC SMP configurations.
parents df6c0cd9 21e9ac7b

arch/mips/Kconfig

+2 −1
Original line number Diff line number Diff line
@@ -408,7 +408,7 @@ config MOMENCO_OCELOT_C 
	select SWAP_IO_SPACE

	select SYS_HAS_CPU_RM7000

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL if BROKEN

	select SYS_SUPPORTS_BIG_ENDIAN

	help

	  The Ocelot is a MIPS-based Single Board Computer (SBC) made by
@@ -1690,6 +1690,7 @@ config NR_CPUS 
	depends on SMP

	default "64" if SGI_IP27

	default "2"

	default "8" if MIPS_MT_SMTC

	help

	  This allows you to specify the maximum number of CPUs which this

	  kernel will support.  The maximum supported value is 32 for 32-bit

arch/mips/au1000/common/time.c

+2 −6
Original line number Diff line number Diff line
@@ -82,7 +82,6 @@ unsigned long wtimer; 
void mips_timer_interrupt(void)

{

	int irq = 63;

	unsigned long count;



	irq_enter();

	kstat_this_cpu.irqs[irq]++;
@@ -231,7 +230,6 @@ wakeup_counter0_set(int ticks) 
 */

unsigned long cal_r4koff(void)

{

	unsigned long count;

	unsigned long cpu_speed;

	unsigned long flags;

	unsigned long counter;
@@ -258,7 +256,7 @@ unsigned long cal_r4koff(void) 


#if defined(CONFIG_AU1000_USE32K)

		{

			unsigned long start, end;

			unsigned long start, end, count;



			start = au_readl(SYS_RTCREAD);

			start += 2;
@@ -282,7 +280,6 @@ unsigned long cal_r4koff(void) 
#else

		cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *

			AU1000_SRC_CLK;

		count = cpu_speed / 2;

#endif

	}

	else {
@@ -291,10 +288,9 @@ unsigned long cal_r4koff(void) 
		 * NOTE: some old silicon doesn't allow reading the PLL.

		 */

		cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;

		count = cpu_speed / 2;

		no_au1xxx_32khz = 1;

	}

	mips_hpt_frequency = count;

	mips_hpt_frequency = cpu_speed;

	// Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)

	set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));

	spin_unlock_irqrestore(&time_lock, flags);

arch/mips/emma2rh/common/irq_emma2rh.c

+1 −1
Original line number Diff line number Diff line
@@ -97,7 +97,7 @@ void emma2rh_irq_init(u32 irq_base) 
		irq_desc[i].status = IRQ_DISABLED;

		irq_desc[i].action = NULL;

		irq_desc[i].depth = 1;

		irq_desc[i].handler = &emma2rh_irq_controller;

		irq_desc[i].chip = &emma2rh_irq_controller;

	}



	emma2rh_irq_base = irq_base;

arch/mips/emma2rh/markeins/irq_markeins.c

+2 −2
Original line number Diff line number Diff line
@@ -86,7 +86,7 @@ void emma2rh_sw_irq_init(u32 irq_base) 
		irq_desc[i].status = IRQ_DISABLED;

		irq_desc[i].action = NULL;

		irq_desc[i].depth = 2;

		irq_desc[i].handler = &emma2rh_sw_irq_controller;

		irq_desc[i].chip = &emma2rh_sw_irq_controller;

	}



	emma2rh_sw_irq_base = irq_base;
@@ -166,7 +166,7 @@ void emma2rh_gpio_irq_init(u32 irq_base) 
		irq_desc[i].status = IRQ_DISABLED;

		irq_desc[i].action = NULL;

		irq_desc[i].depth = 2;

		irq_desc[i].handler = &emma2rh_gpio_irq_controller;

		irq_desc[i].chip = &emma2rh_gpio_irq_controller;

	}



	emma2rh_gpio_irq_base = irq_base;

arch/mips/emma2rh/markeins/platform.c

+56 −32
Original line number Diff line number Diff line
@@ -44,18 +44,45 @@ 
#define I2C_EMMA2RH "emma2rh-iic" /* must be in sync with IIC driver */



static struct resource i2c_emma_resources_0[] = {

	{ NULL, EMMA2RH_IRQ_PIIC0, EMMA2RH_IRQ_PIIC0, IORESOURCE_IRQ },

	{ NULL, KSEG1ADDR(EMMA2RH_PIIC0_BASE), KSEG1ADDR(EMMA2RH_PIIC0_BASE + 0x1000), 0 },

	{

		.name	= NULL,

		.start	= EMMA2RH_IRQ_PIIC0,

		.end	= EMMA2RH_IRQ_PIIC0,

		.flags	= IORESOURCE_IRQ

	}, {

		.name	= NULL,

		.start	= EMMA2RH_PIIC0_BASE,

		.end	= EMMA2RH_PIIC0_BASE + 0x1000,

		.flags	= 0

	},

};



struct resource i2c_emma_resources_1[] = {

	{ NULL, EMMA2RH_IRQ_PIIC1, EMMA2RH_IRQ_PIIC1, IORESOURCE_IRQ },

	{ NULL, KSEG1ADDR(EMMA2RH_PIIC1_BASE), KSEG1ADDR(EMMA2RH_PIIC1_BASE + 0x1000), 0 },

	{

		.name	= NULL,

		.start	= EMMA2RH_IRQ_PIIC1,

		.end	= EMMA2RH_IRQ_PIIC1,

		.flags	= IORESOURCE_IRQ

	}, {

		.name	= NULL,

		.start	= EMMA2RH_PIIC1_BASE,

		.end	= EMMA2RH_PIIC1_BASE + 0x1000,

		.flags	= 0

	},

};



struct resource i2c_emma_resources_2[] = {

	{ NULL, EMMA2RH_IRQ_PIIC2, EMMA2RH_IRQ_PIIC2, IORESOURCE_IRQ },

	{ NULL, KSEG1ADDR(EMMA2RH_PIIC2_BASE), KSEG1ADDR(EMMA2RH_PIIC2_BASE + 0x1000), 0 },

	{

		.name	= NULL,

		.start	= EMMA2RH_IRQ_PIIC2,

		.end	= EMMA2RH_IRQ_PIIC2,

		.flags	= IORESOURCE_IRQ

	}, {

		.name	= NULL,

		.start	= EMMA2RH_PIIC2_BASE,

		.end	= EMMA2RH_PIIC2_BASE + 0x1000,

		.flags	= 0

	},

};



struct platform_device i2c_emma_devices[] = {
@@ -90,24 +117,21 @@ static struct plat_serial8250_port platform_serial_ports[] = { 
		.regshift = 4,

		.iotype = UPIO_MEM,

		.flags = EMMA2RH_SERIAL_FLAGS,

       },

       [1] = {

       }, [1] = {

		.membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3),

		.irq = EMMA2RH_IRQ_PFUR1,

		.uartclk = EMMA2RH_SERIAL_CLOCK,

		.regshift = 4,

		.iotype = UPIO_MEM,

		.flags = EMMA2RH_SERIAL_FLAGS,

       },

       [2] = {

       }, [2] = {

		.membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3),

		.irq = EMMA2RH_IRQ_PFUR2,

		.uartclk = EMMA2RH_SERIAL_CLOCK,

		.regshift = 4,

		.iotype = UPIO_MEM,

		.flags = EMMA2RH_SERIAL_FLAGS,

       },

       [3] = {

       }, [3] = {

		.flags = 0,

       },

};