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Commit 4e01a914 authored by marc0601's avatar marc0601
Browse files

fixes

parent bfd6c08d

arch/arm/configs/n7100_defconfig

+4 −5
Original line number Diff line number Diff line
@@ -42,8 +42,8 @@ CONFIG_LOCALVERSION_AUTO=y 
CONFIG_HAVE_KERNEL_GZIP=y

CONFIG_HAVE_KERNEL_LZMA=y

CONFIG_HAVE_KERNEL_LZO=y

CONFIG_KERNEL_GZIP=y

# CONFIG_KERNEL_LZMA is not set

# CONFIG_KERNEL_GZIP is not set

CONFIG_KERNEL_LZMA=y

# CONFIG_KERNEL_LZO is not set

CONFIG_DEFAULT_HOSTNAME="(none)"

CONFIG_SWAP=y
@@ -105,7 +105,6 @@ CONFIG_INITRAMFS_SOURCE="" 
CONFIG_RD_GZIP=y

# CONFIG_RD_BZIP2 is not set

# CONFIG_RD_LZMA is not set

# CONFIG_RD_XZ is not set

# CONFIG_RD_LZO is not set

# CONFIG_RD_LZ4 is not set

# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -755,7 +754,7 @@ CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART=y 
# CONFIG_USE_OF is not set

CONFIG_ZBOOT_ROM_TEXT=0

CONFIG_ZBOOT_ROM_BSS=0

CONFIG_CMDLINE="console=ttySAC2,115200 consoleblank=0 androidboot.hardware=smdk4x12 androidboot.selinux=permissive"

CONFIG_CMDLINE="console=ttySAC2,115200 consoleblank=0 androidboot.hardware=smdk4x12"

# CONFIG_CMDLINE_FROM_BOOTLOADER is not set

CONFIG_CMDLINE_EXTEND=y

# CONFIG_CMDLINE_FORCE is not set
@@ -2352,7 +2351,7 @@ CONFIG_FB_S5P_NR_BUFFERS=2 
CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD=8192

CONFIG_FB_S5P_MDNIE=y

# CONFIG_FB_MDNIE_PWM is not set

CONFIG_FB_MDNIE_RGB_ADJUST=y

# CONFIG_FB_MDNIE_RGB_ADJUST is not set

CONFIG_FB_S5P_MIPI_DSIM=y

CONFIG_FB_BGRA_ORDER=y

# CONFIG_FB_RGBA_ORDER is not set

arch/arm/mach-exynos/cpufreq-4x12.c

+20 −260
Original line number Diff line number Diff line
@@ -45,7 +45,6 @@ struct cpufreq_clkdiv { 


static unsigned int exynos4x12_volt_table[CPUFREQ_LEVEL_END];



#ifdef CONFIG_MACH_T0

static struct cpufreq_frequency_table exynos4x12_freq_table[] = {

	{L0, 2000*1000},

	{L1, 1902*1000},
@@ -70,30 +69,6 @@ static struct cpufreq_frequency_table exynos4x12_freq_table[] = { 
	{0, CPUFREQ_TABLE_END},

};



#else

static struct cpufreq_frequency_table exynos4x12_freq_table[] = {

	{L0, 1800*1000},

	{L1, 1704*1000},

	{L2, 1600*1000},

	{L3, 1500*1000},

	{L4, 1400*1000},

	{L5, 1300*1000},

	{L6, 1200*1000},

	{L7, 1100*1000},

	{L8, 1000*1000},

	{L9, 900*1000},

	{L10, 800*1000},

	{L11, 700*1000},

	{L12, 600*1000},

	{L13, 500*1000},

	{L14, 400*1000},

	{L15, 300*1000},

	{L16, 200*1000},

	{L17, 100*1000},

	{0, CPUFREQ_TABLE_END},

};

#endif



static struct cpufreq_clkdiv exynos4x12_clkdiv_table[CPUFREQ_LEVEL_END];



static unsigned int clkdiv_cpu0_4212[CPUFREQ_LEVEL_END][8] = {
@@ -157,8 +132,6 @@ static unsigned int clkdiv_cpu0_4212[CPUFREQ_LEVEL_END][8] = { 
	{ 0, 1, 3, 0, 1, 1, 1, 0 },

};





#ifdef CONFIG_MACH_T0

static unsigned int clkdiv_cpu0_4412[CPUFREQ_LEVEL_END][8] = {

	/*

	 * Clock divider value for following
@@ -227,69 +200,6 @@ static unsigned int clkdiv_cpu0_4412[CPUFREQ_LEVEL_END][8] = { 
	{ 0, 1, 3, 0, 1, 1, 1, 0 },

};



#else

static unsigned int clkdiv_cpu0_4412[CPUFREQ_LEVEL_END][8] = {

	/*

	 * Clock divider value for following

	 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,

	 *		DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 }

	 */

	/* ARM L0: 1800Mhz */

	{ 0, 4, 7, 0, 7, 1, 7, 0 },



	/* ARM L1: 1704Mhz */

	{ 0, 4, 7, 0, 7, 1, 7, 0 },



	/* ARM L2: 1600Mhz */

	{ 0, 4, 7, 0, 7, 1, 7, 0 },



	/* ARM L3: 1500Mhz */

	{ 0, 4, 7, 0, 7, 1, 7, 0 },



	/* ARM L4: 1400Mhz */

	{ 0, 3, 7, 0, 6, 1, 7, 0 },



	/* ARM L5: 1300Mhz */

	{ 0, 3, 7, 0, 6, 1, 6, 0 },



	/* ARM L6: 1200Mhz */

	{ 0, 3, 7, 0, 5, 1, 6, 0 },



	/* ARM L7: 1100Mhz */

	{ 0, 3, 7, 0, 5, 1, 5, 0 },



	/* ARM L8: 1000MHz */

	{ 0, 3, 6, 0, 4, 1, 5, 0 },



	/* ARM L9: 900MHz */

	{ 0, 2, 5, 0, 4, 1, 4, 0 },



	/* ARM L10: 800MHz */

	{ 0, 2, 5, 0, 3, 1, 4, 0 },



	/* ARM L11: 700MHz */

	{ 0, 2, 5, 0, 3, 1, 3, 0 },



	/* ARM L12: 600MHz */

	{ 0, 2, 4, 0, 3, 1, 3, 0 },



	/* ARM L13: 500MHz */

	{ 0, 2, 4, 0, 3, 1, 2, 0 },



	/* ARM L14: 400MHz */

	{ 0, 2, 4, 0, 3, 1, 2, 0 },



	/* ARM L15: 300MHz */

	{ 0, 2, 4, 0, 3, 1, 1, 0 },



	/* ARM L16: 200MHz */

	{ 0, 2, 4, 0, 2, 1, 1, 0 },



	/* ARM L17: 100MHz */

	{ 0, 1, 3, 0, 1, 1, 1, 0 },

};

#endif





static unsigned int clkdiv_cpu1_4212[CPUFREQ_LEVEL_END][2] = {

	/* Clock divider value for following
@@ -351,8 +261,6 @@ static unsigned int clkdiv_cpu1_4212[CPUFREQ_LEVEL_END][2] = { 
	{ 2, 0 },

};





#ifdef CONFIG_MACH_T0

static unsigned int clkdiv_cpu1_4412[CPUFREQ_LEVEL_END][3] = {

	/* Clock divider value for following

	 * { DIVCOPY, DIVHPM, DIVCORES }
@@ -419,70 +327,6 @@ static unsigned int clkdiv_cpu1_4412[CPUFREQ_LEVEL_END][3] = { 
	{ 1, 0, 0 },

};



#else

static unsigned int clkdiv_cpu1_4412[CPUFREQ_LEVEL_END][3] = {

	/* Clock divider value for following

	 * { DIVCOPY, DIVHPM, DIVCORES }

	 */



	/* ARM L0: 1800MHz */

	{ 7, 0, 7 },



	/* ARM L1: 1704MHz */

	{ 7, 0, 7 },



	/* ARM L2: 1600MHz */

	{ 7, 0, 7 },



	/* ARM L3: 1500MHz */

	{ 7, 0, 7 },



	/* ARM L4: 1400MHz */

	{ 6, 0, 7 },



	/* ARM L5: 1300MHz */

	{ 6, 0, 6 },



	/* ARM L6: 1200MHz */

	{ 5, 0, 6 },



	/* ARM L7: 1100MHz */

	{ 5, 0, 5 },



	/* ARM L8: 1000MHz */

	{ 4, 0, 5 },



	/* ARM L9: 900MHz */

	{ 4, 0, 4 },



	/* ARM L10: 800MHz */

	{ 3, 0, 4 },



	/* ARM L11: 700MHz */

	{ 3, 0, 3 },



	/* ARM L12: 600MHz */

	{ 3, 0, 3 },



	/* ARM L13: 500MHz */

	{ 3, 0, 2 },



	/* ARM L14: 400MHz */

	{ 3, 0, 2 },



	/* ARM L15: 300MHz */

	{ 3, 0, 1 },



	/* ARM L16: 200MHz */

	{ 3, 0, 0 },



	/* ARM L17: 100MHz */

	{ 1, 0, 0 },

};

#endif

 

#ifdef CONFIG_MACH_T0



static unsigned int exynos4x12_apll_pms_table[CPUFREQ_LEVEL_END] = {

	/* APLL FOUT L0: 2000MHz */

	((250<<16)|(3<<8)|(0x0)),
@@ -545,65 +389,6 @@ static unsigned int exynos4x12_apll_pms_table[CPUFREQ_LEVEL_END] = { 
    ((100<<16)|(3<<8)|(0x3)),

};



#else

static unsigned int exynos4x12_apll_pms_table[CPUFREQ_LEVEL_END] = {



   /* APLL FOUT L0: 1800MHz */

    ((300<<16)|(4<<8)|(0x0)),



	/* APLL FOUT L1: 1704MHz */

	((213<<16)|(3<<8)|(0x0)),



	/* APLL FOUT L2: 1600MHz */

	((200<<16)|(3<<8)|(0x0)),



	/* APLL FOUT L3: 1500MHz */

    ((250<<16)|(4<<8)|(0x0)),



	/* APLL FOUT L4: 1400MHz */

	((175<<16)|(3<<8)|(0x0)),



	/* APLL FOUT L5: 1300MHz */

	((325<<16)|(6<<8)|(0x0)),



	/* APLL FOUT L6: 1200MHz */

	((200<<16)|(4<<8)|(0x0)),



	/* APLL FOUT L7: 1100MHz */

	((275<<16)|(6<<8)|(0x0)),



	/* APLL FOUT L8: 1000MHz */

	((125<<16)|(3<<8)|(0x0)),



	/* APLL FOUT L9: 900MHz */

	((150<<16)|(4<<8)|(0x0)),



	/* APLL FOUT L10: 800MHz */

	((100<<16)|(3<<8)|(0x0)),



	/* APLL FOUT L11: 700MHz */

	((175<<16)|(3<<8)|(0x1)),



	/* APLL FOUT L12: 600MHz */

	((200<<16)|(4<<8)|(0x1)),



	/* APLL FOUT L13: 500MHz */

	((125<<16)|(3<<8)|(0x1)),



	/* APLL FOUT L14 400MHz */

	((100<<16)|(3<<8)|(0x1)),



	/* APLL FOUT L15: 300MHz */

	((200<<16)|(4<<8)|(0x2)),



	/* APLL FOUT L16: 200MHz */

	((100<<16)|(3<<8)|(0x2)),



    /* APLL FOUT L17: 100MHz */

    ((100<<16)|(3<<8)|(0x3)),

};

#endif



/*

 * ASV group voltage table

 */
@@ -638,7 +423,6 @@ static const unsigned int asv_voltage_s[CPUFREQ_LEVEL_END] = { 
};



/* ASV table for 12.5mV step */

#ifdef CONFIG_MACH_T0

static const unsigned int asv_voltage_step_12_5[CPUFREQ_LEVEL_END][12] = {

	/*   ASV0,    ASV1,    ASV2,    ASV3,	 ASV4,	  ASV5,	   ASV6,    ASV7,    ASV8,    ASV9,   ASV10,   ASV11 */

	{ 1475000, 1475000, 1475000, 1475000, 1475000, 1475000, 1475000, 1475000, 1475000, 1475000, 1475000, 1475000 }, /* 2000MHz */
@@ -663,53 +447,29 @@ static const unsigned int asv_voltage_step_12_5[CPUFREQ_LEVEL_END][12] = { 
	{  850000,  837500,  825000,  825000,  825000,  825000,  825000,  825000,  812500,  800000,  800000,  787500 },

};



#else

static const unsigned int asv_voltage_step_12_5[CPUFREQ_LEVEL_END][12] = {

	/*   ASV0,    ASV1,    ASV2,    ASV3,	 ASV4,	  ASV5,	   ASV6,    ASV7,    ASV8,    ASV9,   ASV10,   ASV11 */



    { 1475000, 1475000, 1475000, 1475000, 1475000, 1450000, 1450000, 1450000, 1450000, 1437500, 1425000, 1412500 }, /* 1800MHz */

    { 1425000, 1425000, 1425000, 1425000, 1425000, 1400000, 1400000, 1400000, 1400000, 1387500, 1375000, 1362500 }, /* 1704MHz */

    { 1425000, 1425000, 1425000, 1425000, 1425000, 1400000, 1400000, 1400000, 1400000, 1387500, 1375000, 1362500 }, /* 1600MHz */

	{ 1400000, 1400000, 1400000, 1400000, 1387500, 1387500, 1375000, 1362500, 1350000, 1337500, 1325000, 1312500 },

	{ 1325000, 1312500, 1300000, 1287500, 1300000, 1287500,	1275000, 1250000, 1250000, 1237500, 1225000, 1212500 },

	{ 1300000, 1275000, 1237500, 1237500, 1250000, 1250000,	1237500, 1212500, 1200000, 1200000, 1187500, 1175000 },

	{ 1225000, 1212500, 1200000, 1187500, 1200000, 1187500,	1175000, 1150000, 1137500, 1125000, 1125000, 1112500 },

	{ 1175000, 1162500, 1150000, 1137500, 1150000, 1137500,	1125000, 1100000, 1100000, 1075000, 1075000, 1062500 },

	{ 1125000, 1112500, 1100000, 1087500, 1100000, 1087500,	1075000, 1050000, 1037500, 1025000, 1025000, 1012500 },

	{ 1075000, 1062500, 1050000, 1050000, 1050000, 1037500,	1025000, 1012500, 1000000,  987500,  987500,  975000 },

	{ 1037500, 1025000, 1000000, 1000000, 1000000,  987500,	 975000,  962500,  962500,  962500,  962500,  950000 },

	{ 1012500, 1000000,  975000,  975000,  975000,  975000,	 962500,  962500,  950000,  950000,  950000,  937500 },

	{ 1000000,  987500,  962500,  962500,  962500,  962500,	 950000,  950000,  937500,  937500,  937500,  925000 },

	{  987500,  975000,  950000,  937500,  950000,  937500,	 937500,  937500,  912500,  912500,  912500,  900000 },

	{  975000,  962500,  950000,  925000,  950000,  925000,	 925000,  925000,  900000,  900000,  900000,  887500 },

	{  950000,  937500,  925000,  900000,  925000,  900000,	 900000,  900000,  900000,  887500,  875000,  862500 },

	{  925000,  912500,  900000,  900000,  900000,  900000,	 900000,  900000,  887500,  875000,  875000,  862500 },

	{  850000,  837500,  825000,  825000,  825000,  825000,  825000,  825000,  812500,  800000,  800000,  787500 },

};



#endif



/* 20120725 DVFS table for pega prime */

static const unsigned int asv_voltage_step_12_5_rev2[CPUFREQ_LEVEL_END][13] = {

	/*   ASV0,    ASV1,    ASV2,    ASV3,	 ASV4,	  ASV5,	   ASV6,    ASV7,    ASV8,    ASV9,   ASV10,   ASV11    ASV12 */

    { 1362500, 1362500, 1362500, 1362500, 1350000, 1337500, 1325000, 1312500, 1300000, 1287500, 1262500, 1250000, 1237500 },    /* L0 */

    { 1312500, 1312500, 1312500, 1312500, 1300000, 1287500, 1275000, 1262500, 1250000, 1237500, 1212500, 1200000, 1187500 },    /* L1 */

    { 1312500, 1312500, 1312500, 1312500, 1300000, 1287500, 1275000, 1262500, 1250000, 1237500, 1212500, 1200000, 1187500 },    /* L2 */

	{ 1275000, 1262500, 1262500, 1262500, 1250000, 1237500,	1225000, 1212500, 1200000, 1187500, 1162500, 1150000, 1137500 },	/* L3 */

	{ 1237500, 1225000, 1225000, 1225000, 1212500, 1200000, 1187500, 1175000, 1162500, 1150000, 1125000, 1112500, 1100000 },	/* L4 */

	{ 1187500, 1175000, 1175000, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, 1075000, 1062500, 1050000 },	/* L5 */

	{ 1150000, 1137500, 1137500, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, 1037500, 1025000, 1012500 },	/* L6 */

	{ 1112500, 1100000, 1100000, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1000000,  987500,  975000 },	/* L7 */

	{ 1087500, 1075000, 1075000, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000,  975000,  962500,  950000 },	/* L8 */

	{ 1062500, 1050000, 1050000, 1050000, 1037500, 1025000, 1012500, 1000000,  987500,  975000,  950000,  937500,  925000 },	/* L9 */

	{ 1025000, 1012500, 1012500, 1012500, 1000000,  987500,  975000,  962500,  950000,  937500,  912500,  900000,  887500 },	/* L10 */

	{ 1000000,  987500,  987500,  987500,  975000,  962500,  950000,  937500,  925000,  912500,  887500,  887500,  887500 },	/* L11 */

	{  975000,  962500,  962500,  962500,  950000,  937500,  925000,  912500,  900000,  887500,  875000,  875000,  875000 },	/* L12 */

	{  962500,  950000,  950000,  950000,  937500,  925000,  912500,  900000,  887500,  887500,  875000,  875000,  875000 },	/* L13 */

	{  950000,  937500,  937500,  937500,  925000,  912500,  900000,  887500,  887500,  887500,  875000,  875000,  875000 },	/* L14 */

	{  937500,  925000,  925000,  925000,  912500,  900000,  887500,  887500,  887500,  887500,  875000,  875000,  875000 },	/* L15 */

	{  925000,  912500,  912500,  912500,  900000,  887500,  887500,  887500,  887500,  887500,  875000,  875000,  875000 },	/* L16 */

	{  850000,  837500,  837500,  837500,  825000,  812500,  812500,  812500,  812500,  812500,  800000,  800000,  800000 }, 	/* L17 */

    { 1450000, 1450000, 1450000, 1450000, 1450000, 1450000, 1450000, 1450000, 1450000, 1450000, 1450000, 1450000, 1450000 }, /* 2000MHz */

    { 1400000, 1375000, 1375000, 1375000, 1375000, 1375000, 1375000, 1375000, 1375000, 1375000, 1375000, 1375000, 1375000 }, /* 1902MHz */

    { 1362500, 1362500, 1362500, 1362500, 1350000, 1337500, 1325000, 1312500, 1300000, 1287500, 1262500, 1250000, 1237500 },    /* L2 */

    { 1312500, 1312500, 1312500, 1312500, 1300000, 1287500, 1275000, 1262500, 1250000, 1237500, 1212500, 1200000, 1187500 },    /* L3 */

    { 1312500, 1312500, 1312500, 1312500, 1300000, 1287500, 1275000, 1262500, 1250000, 1237500, 1212500, 1200000, 1187500 },    /* L4 */

    { 1275000, 1262500, 1262500, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000, 1187500, 1162500, 1150000, 1137500 },    /* L5 */

    { 1237500, 1225000, 1225000, 1225000, 1212500, 1200000, 1187500, 1175000, 1162500, 1150000, 1125000, 1112500, 1100000 },	/* L6 */

    { 1187500, 1175000, 1175000, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, 1075000, 1062500, 1050000 },	/* L7 */

    { 1150000, 1137500, 1137500, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, 1037500, 1025000, 1012500 },	/* L8 */

    { 1112500, 1100000, 1100000, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1000000,  987500,  975000 },	/* L9 */

    { 1087500, 1075000, 1075000, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000,  975000,  962500,  950000 },	/* L10 */

    { 1062500, 1050000, 1050000, 1050000, 1037500, 1025000, 1012500, 1000000,  987500,  975000,  950000,  937500,  925000 },	/* L11 */

    { 1025000, 1012500, 1012500, 1012500, 1000000,  987500,  975000,  962500,  950000,  937500,  912500,  900000,  887500 },	/* L12 */

    { 1000000,  987500,  987500,  987500,  975000,  962500,  950000,  937500,  925000,  912500,  887500,  887500,  887500 },	/* L13 */

    {  975000,  962500,  962500,  962500,  950000,  937500,  925000,  912500,  900000,  887500,  875000,  875000,  875000 },	/* L14 */

    {  962500,  950000,  950000,  950000,  937500,  925000,  912500,  900000,  887500,  887500,  875000,  875000,  875000 },	/* L15 */

    {  950000,  937500,  937500,  937500,  925000,  912500,  900000,  887500,  887500,  887500,  875000,  875000,  875000 },	/* L16 */

    {  937500,  925000,  925000,  925000,  912500,  900000,  887500,  887500,  887500,  887500,  875000,  875000,  875000 },	/* L17 */

    {  925000,  912500,  912500,  912500,  900000,  887500,  887500,  887500,  887500,  887500,  875000,  875000,  875000 },    /* L18 */

    {  850000,  837500,  837500,  837500,  825000,  812500,  812500,  812500,  812500,  812500,  800000,  800000,  800000 }, 	/* L19 */

};



static const unsigned int asv_voltage_step_1ghz[CPUFREQ_LEVEL_END][12] = {

arch/arm/mach-exynos/cpufreq.c

+1 −6
Original line number Diff line number Diff line
@@ -755,13 +755,8 @@ static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy) 
	ret = cpufreq_frequency_table_cpuinfo(policy, exynos_info->freq_table);

	

	/* Set default startup frq. */

#ifdef CONFIG_MACH_T0

	policy->max = 1600000;

	policy->min = 100000;

#else

	policy->max = 1400000;

	policy->min = 100000;

#endif

	policy->min = 200000;



	if (ret)

		return ret;

drivers/cpufreq/cpufreq_intelliactive.c

+64 −184

File changed.

Preview size limit exceeded, changes collapsed.

drivers/cpufreq/cpufreq_interactive.c

+6 −67
Original line number Diff line number Diff line
@@ -30,7 +30,6 @@ 
#include <linux/kthread.h>

#include <linux/slab.h>

#include <linux/kernel_stat.h>

#include <linux/earlysuspend.h>

#include <asm/cputime.h>



static int active_count;
@@ -57,9 +56,6 @@ struct cpufreq_interactive_cpuinfo { 


static DEFINE_PER_CPU(struct cpufreq_interactive_cpuinfo, cpuinfo);



/* boolean for determining screen on/off state */

static bool suspended = false;



/* realtime thread handles frequency scaling */

static struct task_struct *speedchange_task;

static cpumask_t speedchange_cpumask;
@@ -401,7 +397,6 @@ static void cpufreq_interactive_timer(unsigned long data) 
	boosted = boost_val || now < boostpulse_endtime;



	if (cpu_load >= go_hispeed_load || boosted) {

		if (pcpu->policy->cpu == 0 && !suspended) {

		if (pcpu->target_freq < hispeed_freq) {

			new_freq = hispeed_freq;

		} else {
@@ -410,7 +405,6 @@ static void cpufreq_interactive_timer(unsigned long data) 
			if (new_freq < hispeed_freq)

				new_freq = hispeed_freq;

		}

		}

	} else {

		new_freq = choose_freq(pcpu, loadadjfreq);

	}
@@ -1054,35 +1048,6 @@ static int cpufreq_interactive_idle_notifier(struct notifier_block *nb, 
	return 0;

}



extern bool is_incall;

static void cpu_up_work(struct work_struct *work)

{

	int cpu;



	for_each_cpu_not(cpu, cpu_online_mask) {

		if (cpu == 0)

			continue;

		cpu_up(cpu);

	}

}



static void cpu_down_work(struct work_struct *work)

{

	int cpu;



	if (is_incall)

		return;



	for_each_online_cpu(cpu) {

		if (cpu == 0)

			continue;

		cpu_down(cpu);

	}

}



static DECLARE_WORK(interactive_up_work, cpu_up_work);

static DECLARE_WORK(interactive_down_work, cpu_down_work);



static struct notifier_block cpufreq_interactive_idle_nb = {

	.notifier_call = cpufreq_interactive_idle_notifier,

};
@@ -1141,8 +1106,6 @@ static int cpufreq_governor_interactive(struct cpufreq_policy *policy, 
			return rc;

		}



		schedule_work_on(0, &interactive_up_work);



		idle_notifier_register(&cpufreq_interactive_idle_nb);

		cpufreq_register_notifier(

			&cpufreq_notifier_block, CPUFREQ_TRANSITION_NOTIFIER);
@@ -1165,8 +1128,6 @@ static int cpufreq_governor_interactive(struct cpufreq_policy *policy, 
			return 0;

		}



		schedule_work_on(0, &interactive_down_work);



		cpufreq_unregister_notifier(

			&cpufreq_notifier_block, CPUFREQ_TRANSITION_NOTIFIER);

		idle_notifier_unregister(&cpufreq_interactive_idle_nb);
@@ -1227,25 +1188,6 @@ static void cpufreq_interactive_nop_timer(unsigned long data) 
{

}



static void interactive_early_suspend(struct early_suspend *handler)

{

	suspended = true;

	schedule_work_on(0, &interactive_down_work);

	return;

}



static void interactive_late_resume(struct early_suspend *handler)

{

	suspended = false;

	schedule_work_on(0, &interactive_up_work);

	return;

}



static struct early_suspend interactive_suspend = {

	.suspend = interactive_early_suspend,

	.resume = interactive_late_resume,

};



static int __init cpufreq_interactive_init(void)

{

	unsigned int i;
@@ -1265,8 +1207,6 @@ static int __init cpufreq_interactive_init(void) 
		init_rwsem(&pcpu->enable_sem);

	}



	register_early_suspend(&interactive_suspend);



	spin_lock_init(&target_loads_lock);

	spin_lock_init(&speedchange_cpumask_lock);

	spin_lock_init(&above_hispeed_delay_lock);
@@ -1294,7 +1234,6 @@ module_init(cpufreq_interactive_init); 


static void __exit cpufreq_interactive_exit(void)

{

	unregister_early_suspend(&interactive_suspend);

	cpufreq_unregister_governor(&cpufreq_gov_interactive);

	kthread_stop(speedchange_task);

	put_task_struct(speedchange_task);