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Commit 93a4ed87 authored by Rafał Miłecki's avatar Rafał Miłecki Committed by Dave Airlie
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drm/radeon/kms: define TMDS/LVTM HDMI enabling bits 



The names has been taken from free M76 specs.

Signed-off-by: default avatarRafał Miłecki <zajec5@gmail.com>
Reviewed-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 92db7f6c

drivers/gpu/drm/radeon/r500_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -573,6 +573,7 @@ 


#define AVIVO_TMDSA_CNTL                    0x7880

#   define AVIVO_TMDSA_CNTL_ENABLE               (1 << 0)

#   define AVIVO_TMDSA_CNTL_HDMI_EN              (1 << 2)

#   define AVIVO_TMDSA_CNTL_HPD_MASK             (1 << 4)

#   define AVIVO_TMDSA_CNTL_HPD_SELECT           (1 << 8)

#   define AVIVO_TMDSA_CNTL_SYNC_PHASE           (1 << 12)
@@ -633,6 +634,7 @@ 


#define AVIVO_LVTMA_CNTL					0x7a80

#   define AVIVO_LVTMA_CNTL_ENABLE               (1 << 0)

#   define AVIVO_LVTMA_CNTL_HDMI_EN              (1 << 2)

#   define AVIVO_LVTMA_CNTL_HPD_MASK             (1 << 4)

#   define AVIVO_LVTMA_CNTL_HPD_SELECT           (1 << 8)

#   define AVIVO_LVTMA_CNTL_SYNC_PHASE           (1 << 12)

drivers/gpu/drm/radeon/r600_hdmi.c

+8 −4
Original line number Diff line number Diff line
@@ -533,11 +533,13 @@ void r600_hdmi_enable(struct drm_encoder *encoder) 
	} else if (rdev->family >= CHIP_R600) {

		switch (radeon_encoder->encoder_id) {

		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:

			WREG32_P(AVIVO_TMDSA_CNTL, 0x4, ~0x4);

			WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN,

				 ~AVIVO_TMDSA_CNTL_HDMI_EN);

			WREG32(offset + R600_HDMI_ENABLE, 0x101);

			break;

		case ENCODER_OBJECT_ID_INTERNAL_LVTM1:

			WREG32_P(AVIVO_LVTMA_CNTL, 0x4, ~0x4);

			WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN,

				 ~AVIVO_LVTMA_CNTL_HDMI_EN);

			WREG32(offset + R600_HDMI_ENABLE, 0x105);

			break;

		default:
@@ -603,11 +605,13 @@ void r600_hdmi_disable(struct drm_encoder *encoder) 
	} else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {

		switch (radeon_encoder->encoder_id) {

		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:

			WREG32_P(AVIVO_TMDSA_CNTL, 0, ~0x4);

			WREG32_P(AVIVO_TMDSA_CNTL, 0,

				 ~AVIVO_TMDSA_CNTL_HDMI_EN);

			WREG32(offset + R600_HDMI_ENABLE, 0);

			break;

		case ENCODER_OBJECT_ID_INTERNAL_LVTM1:

			WREG32_P(AVIVO_LVTMA_CNTL, 0, ~0x4);

			WREG32_P(AVIVO_LVTMA_CNTL, 0,

				 ~AVIVO_LVTMA_CNTL_HDMI_EN);

			WREG32(offset + R600_HDMI_ENABLE, 0);

			break;

		default: