Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8634bd4a authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: Remove regfile code&data for UMS suspend/resume 



Lots of lines to remove!

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
[danvet: Fixup makefile.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 1d03184c

drivers/gpu/drm/i915/Makefile

+1 −2
Original line number Diff line number Diff line
@@ -87,8 +87,7 @@ i915-y += dvo_ch7017.o \ 
i915-y += i915_vgpu.o



# legacy horrors

i915-y += i915_dma.o \

	  i915_ums.o

i915-y += i915_dma.o



obj-$(CONFIG_DRM_I915)  += i915.o

drivers/gpu/drm/i915/i915_drv.h

+0 −133
Original line number Diff line number Diff line
@@ -900,150 +900,21 @@ struct intel_gmbus { 
};



struct i915_suspend_saved_registers {

	u8 saveLBB;

	u32 saveDSPACNTR;

	u32 saveDSPBCNTR;

	u32 saveDSPARB;

	u32 savePIPEACONF;

	u32 savePIPEBCONF;

	u32 savePIPEASRC;

	u32 savePIPEBSRC;

	u32 saveFPA0;

	u32 saveFPA1;

	u32 saveDPLL_A;

	u32 saveDPLL_A_MD;

	u32 saveHTOTAL_A;

	u32 saveHBLANK_A;

	u32 saveHSYNC_A;

	u32 saveVTOTAL_A;

	u32 saveVBLANK_A;

	u32 saveVSYNC_A;

	u32 saveBCLRPAT_A;

	u32 saveTRANSACONF;

	u32 saveTRANS_HTOTAL_A;

	u32 saveTRANS_HBLANK_A;

	u32 saveTRANS_HSYNC_A;

	u32 saveTRANS_VTOTAL_A;

	u32 saveTRANS_VBLANK_A;

	u32 saveTRANS_VSYNC_A;

	u32 savePIPEASTAT;

	u32 saveDSPASTRIDE;

	u32 saveDSPASIZE;

	u32 saveDSPAPOS;

	u32 saveDSPAADDR;

	u32 saveDSPASURF;

	u32 saveDSPATILEOFF;

	u32 savePFIT_PGM_RATIOS;

	u32 saveBLC_HIST_CTL;

	u32 saveBLC_PWM_CTL;

	u32 saveBLC_PWM_CTL2;

	u32 saveBLC_CPU_PWM_CTL;

	u32 saveBLC_CPU_PWM_CTL2;

	u32 saveFPB0;

	u32 saveFPB1;

	u32 saveDPLL_B;

	u32 saveDPLL_B_MD;

	u32 saveHTOTAL_B;

	u32 saveHBLANK_B;

	u32 saveHSYNC_B;

	u32 saveVTOTAL_B;

	u32 saveVBLANK_B;

	u32 saveVSYNC_B;

	u32 saveBCLRPAT_B;

	u32 saveTRANSBCONF;

	u32 saveTRANS_HTOTAL_B;

	u32 saveTRANS_HBLANK_B;

	u32 saveTRANS_HSYNC_B;

	u32 saveTRANS_VTOTAL_B;

	u32 saveTRANS_VBLANK_B;

	u32 saveTRANS_VSYNC_B;

	u32 savePIPEBSTAT;

	u32 saveDSPBSTRIDE;

	u32 saveDSPBSIZE;

	u32 saveDSPBPOS;

	u32 saveDSPBADDR;

	u32 saveDSPBSURF;

	u32 saveDSPBTILEOFF;

	u32 saveVGA0;

	u32 saveVGA1;

	u32 saveVGA_PD;

	u32 saveVGACNTRL;

	u32 saveADPA;

	u32 saveLVDS;

	u32 savePP_ON_DELAYS;

	u32 savePP_OFF_DELAYS;

	u32 saveDVOA;

	u32 saveDVOB;

	u32 saveDVOC;

	u32 savePP_ON;

	u32 savePP_OFF;

	u32 savePP_CONTROL;

	u32 savePP_DIVISOR;

	u32 savePFIT_CONTROL;

	u32 save_palette_a[256];

	u32 save_palette_b[256];

	u32 saveFBC_CONTROL;

	u32 saveIER;

	u32 saveIIR;

	u32 saveIMR;

	u32 saveDEIER;

	u32 saveDEIMR;

	u32 saveGTIER;

	u32 saveGTIMR;

	u32 saveFDI_RXA_IMR;

	u32 saveFDI_RXB_IMR;

	u32 saveCACHE_MODE_0;

	u32 saveMI_ARB_STATE;

	u32 saveSWF0[16];

	u32 saveSWF1[16];

	u32 saveSWF2[3];

	u8 saveMSR;

	u8 saveSR[8];

	u8 saveGR[25];

	u8 saveAR_INDEX;

	u8 saveAR[21];

	u8 saveDACMASK;

	u8 saveCR[37];

	uint64_t saveFENCE[I915_MAX_NUM_FENCES];

	u32 saveCURACNTR;

	u32 saveCURAPOS;

	u32 saveCURABASE;

	u32 saveCURBCNTR;

	u32 saveCURBPOS;

	u32 saveCURBBASE;

	u32 saveCURSIZE;

	u32 saveDP_B;

	u32 saveDP_C;

	u32 saveDP_D;

	u32 savePIPEA_GMCH_DATA_M;

	u32 savePIPEB_GMCH_DATA_M;

	u32 savePIPEA_GMCH_DATA_N;

	u32 savePIPEB_GMCH_DATA_N;

	u32 savePIPEA_DP_LINK_M;

	u32 savePIPEB_DP_LINK_M;

	u32 savePIPEA_DP_LINK_N;

	u32 savePIPEB_DP_LINK_N;

	u32 saveFDI_RXA_CTL;

	u32 saveFDI_TXA_CTL;

	u32 saveFDI_RXB_CTL;

	u32 saveFDI_TXB_CTL;

	u32 savePFA_CTL_1;

	u32 savePFB_CTL_1;

	u32 savePFA_WIN_SZ;

	u32 savePFB_WIN_SZ;

	u32 savePFA_WIN_POS;

	u32 savePFB_WIN_POS;

	u32 savePCH_DREF_CONTROL;

	u32 saveDISP_ARB_CTL;

	u32 savePIPEA_DATA_M1;

	u32 savePIPEA_DATA_N1;

	u32 savePIPEA_LINK_M1;

	u32 savePIPEA_LINK_N1;

	u32 savePIPEB_DATA_M1;

	u32 savePIPEB_DATA_N1;

	u32 savePIPEB_LINK_M1;

	u32 savePIPEB_LINK_N1;

	u32 saveMCHBAR_RENDER_STANDBY;

	u32 savePCH_PORT_HOTPLUG;

	u16 saveGCDGMBUS;

};
@@ -3137,10 +3008,6 @@ int i915_parse_cmds(struct intel_engine_cs *ring, 
extern int i915_save_state(struct drm_device *dev);

extern int i915_restore_state(struct drm_device *dev);



/* i915_ums.c */

void i915_save_display_reg(struct drm_device *dev);

void i915_restore_display_reg(struct drm_device *dev);



/* i915_sysfs.c */

void i915_setup_sysfs(struct drm_device *dev_priv);

void i915_teardown_sysfs(struct drm_device *dev_priv);

drivers/gpu/drm/i915/i915_suspend.c

+2 −213
Original line number Diff line number Diff line
@@ -29,166 +29,6 @@ 
#include "intel_drv.h"

#include "i915_reg.h"



static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	I915_WRITE8(index_port, reg);

	return I915_READ8(data_port);

}



static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	I915_READ8(st01);

	I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);

	return I915_READ8(VGA_AR_DATA_READ);

}



static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	I915_READ8(st01);

	I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);

	I915_WRITE8(VGA_AR_DATA_WRITE, val);

}



static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	I915_WRITE8(index_port, reg);

	I915_WRITE8(data_port, val);

}



static void i915_save_vga(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int i;

	u16 cr_index, cr_data, st01;



	/* VGA state */

	dev_priv->regfile.saveVGA0 = I915_READ(VGA0);

	dev_priv->regfile.saveVGA1 = I915_READ(VGA1);

	dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);

	dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));



	/* VGA color palette registers */

	dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);



	/* MSR bits */

	dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);

	if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {

		cr_index = VGA_CR_INDEX_CGA;

		cr_data = VGA_CR_DATA_CGA;

		st01 = VGA_ST01_CGA;

	} else {

		cr_index = VGA_CR_INDEX_MDA;

		cr_data = VGA_CR_DATA_MDA;

		st01 = VGA_ST01_MDA;

	}



	/* CRT controller regs */

	i915_write_indexed(dev, cr_index, cr_data, 0x11,

			   i915_read_indexed(dev, cr_index, cr_data, 0x11) &

			   (~0x80));

	for (i = 0; i <= 0x24; i++)

		dev_priv->regfile.saveCR[i] =

			i915_read_indexed(dev, cr_index, cr_data, i);

	/* Make sure we don't turn off CR group 0 writes */

	dev_priv->regfile.saveCR[0x11] &= ~0x80;



	/* Attribute controller registers */

	I915_READ8(st01);

	dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);

	for (i = 0; i <= 0x14; i++)

		dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);

	I915_READ8(st01);

	I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);

	I915_READ8(st01);



	/* Graphics controller registers */

	for (i = 0; i < 9; i++)

		dev_priv->regfile.saveGR[i] =

			i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);



	dev_priv->regfile.saveGR[0x10] =

		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);

	dev_priv->regfile.saveGR[0x11] =

		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);

	dev_priv->regfile.saveGR[0x18] =

		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);



	/* Sequencer registers */

	for (i = 0; i < 8; i++)

		dev_priv->regfile.saveSR[i] =

			i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);

}



static void i915_restore_vga(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int i;

	u16 cr_index, cr_data, st01;



	/* VGA state */

	I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL);



	I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);

	I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);

	I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);

	POSTING_READ(VGA_PD);

	udelay(150);



	/* MSR bits */

	I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);

	if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {

		cr_index = VGA_CR_INDEX_CGA;

		cr_data = VGA_CR_DATA_CGA;

		st01 = VGA_ST01_CGA;

	} else {

		cr_index = VGA_CR_INDEX_MDA;

		cr_data = VGA_CR_DATA_MDA;

		st01 = VGA_ST01_MDA;

	}



	/* Sequencer registers, don't write SR07 */

	for (i = 0; i < 7; i++)

		i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,

				   dev_priv->regfile.saveSR[i]);



	/* CRT controller regs */

	/* Enable CR group 0 writes */

	i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);

	for (i = 0; i <= 0x24; i++)

		i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);



	/* Graphics controller regs */

	for (i = 0; i < 9; i++)

		i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,

				   dev_priv->regfile.saveGR[i]);



	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,

			   dev_priv->regfile.saveGR[0x10]);

	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,

			   dev_priv->regfile.saveGR[0x11]);

	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,

			   dev_priv->regfile.saveGR[0x18]);



	/* Attribute controller registers */

	I915_READ8(st01); /* switch back to index mode */

	for (i = 0; i <= 0x14; i++)

		i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);

	I915_READ8(st01); /* switch back to index mode */

	I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20);

	I915_READ8(st01);



	/* VGA color palette registers */

	I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);

}



static void i915_save_display(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -197,11 +37,6 @@ static void i915_save_display(struct drm_device *dev) 
	if (INTEL_INFO(dev)->gen <= 4)

		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);



	/* This is only meaningful in non-KMS mode */

	/* Don't regfile.save them in KMS mode */

	if (!drm_core_check_feature(dev, DRIVER_MODESET))

		i915_save_display_reg(dev);



	/* LVDS state */

	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))

		dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
@@ -224,9 +59,6 @@ static void i915_save_display(struct drm_device *dev) 
	/* save FBC interval */

	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))

		dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);



	if (!drm_core_check_feature(dev, DRIVER_MODESET))

		i915_save_vga(dev);

}



static void i915_restore_display(struct drm_device *dev)
@@ -238,10 +70,6 @@ static void i915_restore_display(struct drm_device *dev) 
	if (INTEL_INFO(dev)->gen <= 4)

		I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);



	if (!drm_core_check_feature(dev, DRIVER_MODESET))

		i915_restore_display_reg(dev);



	if (drm_core_check_feature(dev, DRIVER_MODESET))

	mask = ~LVDS_PORT_EN;



	/* LVDS state */
@@ -270,9 +98,6 @@ static void i915_restore_display(struct drm_device *dev) 
	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))

		I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);



	if (!drm_core_check_feature(dev, DRIVER_MODESET))

		i915_restore_vga(dev);

	else

	i915_redisable_vga(dev);

}
@@ -285,24 +110,6 @@ int i915_save_state(struct drm_device *dev) 


	i915_save_display(dev);



	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {

		/* Interrupt state */

		if (HAS_PCH_SPLIT(dev)) {

			dev_priv->regfile.saveDEIER = I915_READ(DEIER);

			dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);

			dev_priv->regfile.saveGTIER = I915_READ(GTIER);

			dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);

			dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);

			dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);

			dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =

				I915_READ(RSTDBYCTL);

			dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);

		} else {

			dev_priv->regfile.saveIER = I915_READ(IER);

			dev_priv->regfile.saveIMR = I915_READ(IMR);

		}

	}



	if (IS_GEN4(dev))

		pci_read_config_word(dev->pdev, GCDGMBUS,

				     &dev_priv->regfile.saveGCDGMBUS);
@@ -341,24 +148,6 @@ int i915_restore_state(struct drm_device *dev) 
				      dev_priv->regfile.saveGCDGMBUS);

	i915_restore_display(dev);



	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {

		/* Interrupt state */

		if (HAS_PCH_SPLIT(dev)) {

			I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);

			I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);

			I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);

			I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);

			I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);

			I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);

			I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);

			I915_WRITE(RSTDBYCTL,

				   dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);

		} else {

			I915_WRITE(IER, dev_priv->regfile.saveIER);

			I915_WRITE(IMR, dev_priv->regfile.saveIMR);

		}

	}



	/* Cache mode state */

	if (INTEL_INFO(dev)->gen < 7)

		I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |

drivers/gpu/drm/i915/i915_ums.c

deleted100644 → 0
+0 −552

File deleted.

Preview size limit exceeded, changes collapsed.