Merge branch 'topic/dw' into for-linus (6df056d8) · Commits · e / devices / android_kernel_samsung_exynos9810

drivers/dma/dw/core.c

+32 −31

Original line number	Diff line number	Diff line
		@@ -1499,9 +1499,8 @@ EXPORT_SYMBOL(dw_dma_cyclic_free);
		int dw_dma_probe(struct dw_dma_chip chip, struct dw_dma_platform_data pdata)
		{
		struct dw_dma *dw;
		bool autocfg;
		bool autocfg = false;
		unsigned int dw_params;
		unsigned int nr_channels;
		unsigned int max_blk_size = 0;
		int err;
		int i;
		@@ -1515,33 +1514,42 @@ int dw_dma_probe(struct dw_dma_chip chip, struct dw_dma_platform_data pdata)

		pm_runtime_get_sync(chip->dev);

		if (!pdata) {
		dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
		autocfg = dw_params >> DW_PARAMS_EN & 0x1;

		dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);

		if (!pdata && autocfg) {
		autocfg = dw_params >> DW_PARAMS_EN & 1;
		if (!autocfg) {
		err = -EINVAL;
		goto err_pdata;
		}

		pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
		if (!pdata) {
		err = -ENOMEM;
		goto err_pdata;
		}

		/* Get hardware configuration parameters */
		pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
		pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
		for (i = 0; i < pdata->nr_masters; i++) {
		pdata->data_width[i] =
		(dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
		}
		max_blk_size = dma_readl(dw, MAX_BLK_SIZE);

		/* Fill platform data with the default values */
		pdata->is_private = true;
		pdata->is_memcpy = true;
		pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
		pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
		} else if (!pdata \|\| pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
		} else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
		err = -EINVAL;
		goto err_pdata;
		}

		if (autocfg)
		nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
		else
		nr_channels = pdata->nr_channels;

		dw->chan = devm_kcalloc(chip->dev, nr_channels, sizeof(*dw->chan),
		dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
		GFP_KERNEL);
		if (!dw->chan) {
		err = -ENOMEM;
		@@ -1549,22 +1557,12 @@ int dw_dma_probe(struct dw_dma_chip chip, struct dw_dma_platform_data pdata)
		}

		/* Get hardware configuration parameters */
		if (autocfg) {
		max_blk_size = dma_readl(dw, MAX_BLK_SIZE);

		dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
		for (i = 0; i < dw->nr_masters; i++) {
		dw->data_width[i] =
		(dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
		}
		} else {
		dw->nr_masters = pdata->nr_masters;
		for (i = 0; i < dw->nr_masters; i++)
		dw->data_width[i] = pdata->data_width[i];
		}

		/* Calculate all channel mask before DMA setup */
		dw->all_chan_mask = (1 << nr_channels) - 1;
		dw->all_chan_mask = (1 << pdata->nr_channels) - 1;

		/* Force dma off, just in case */
		dw_dma_off(dw);
		@@ -1589,7 +1587,7 @@ int dw_dma_probe(struct dw_dma_chip chip, struct dw_dma_platform_data pdata)
		goto err_pdata;

		INIT_LIST_HEAD(&dw->dma.channels);
		for (i = 0; i < nr_channels; i++) {
		for (i = 0; i < pdata->nr_channels; i++) {
		struct dw_dma_chan *dwc = &dw->chan[i];
		int r = nr_channels - i - 1;

		@@ -1603,7 +1601,7 @@ int dw_dma_probe(struct dw_dma_chip chip, struct dw_dma_platform_data pdata)

		/* 7 is highest priority & 0 is lowest. */
		if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
		dwc->priority = r;
		dwc->priority = pdata->nr_channels - i - 1;
		else
		dwc->priority = i;

		@@ -1656,10 +1654,13 @@ int dw_dma_probe(struct dw_dma_chip chip, struct dw_dma_platform_data pdata)
		dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
		dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);

		dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
		/* Set capabilities */
		dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
		if (pdata->is_private)
		dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
		if (pdata->is_memcpy)
		dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);

		dw->dma.dev = chip->dev;
		dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
		dw->dma.device_free_chan_resources = dwc_free_chan_resources;
		@@ -1687,7 +1688,7 @@ int dw_dma_probe(struct dw_dma_chip chip, struct dw_dma_platform_data pdata)
		goto err_dma_register;

		dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
		nr_channels);
		pdata->nr_channels);

		pm_runtime_put_sync_suspend(chip->dev);

drivers/dma/dw/platform.c

+16 −1

Original line number	Diff line number	Diff line
		@@ -155,6 +155,7 @@ static int dw_probe(struct platform_device *pdev)
		struct dw_dma_chip *chip;
		struct device *dev = &pdev->dev;
		struct resource *mem;
		const struct acpi_device_id *id;
		struct dw_dma_platform_data *pdata;
		int err;

		@@ -178,6 +179,11 @@ static int dw_probe(struct platform_device *pdev)
		pdata = dev_get_platdata(dev);
		if (!pdata)
		pdata = dw_dma_parse_dt(pdev);
		if (!pdata && has_acpi_companion(dev)) {
		id = acpi_match_device(dev->driver->acpi_match_table, dev);
		if (id)
		pdata = (struct dw_dma_platform_data *)id->driver_data;
		}

		chip->dev = dev;

		@@ -246,8 +252,17 @@ MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
		#endif

		#ifdef CONFIG_ACPI
		static struct dw_dma_platform_data dw_dma_acpi_pdata = {
		.nr_channels = 8,
		.is_private = true,
		.chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
		.chan_priority = CHAN_PRIORITY_ASCENDING,
		.block_size = 4095,
		.nr_masters = 2,
		};

		static const struct acpi_device_id dw_dma_acpi_id_table[] = {
		{ "INTL9C60", 0 },
		{ "INTL9C60", (kernel_ulong_t)&dw_dma_acpi_pdata },
		{ }
		};
		MODULE_DEVICE_TABLE(acpi, dw_dma_acpi_id_table);

include/linux/platform_data/dma-dw.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -37,6 +37,7 @@ struct dw_dma_slave {
		* @nr_channels: Number of channels supported by hardware (max 8)
		* @is_private: The device channels should be marked as private and not for
		* by the general purpose DMA channel allocator.
		* @is_memcpy: The device channels do support memory-to-memory transfers.
		* @chan_allocation_order: Allocate channels starting from 0 or 7
		* @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
		* @block_size: Maximum block size supported by the controller
		@@ -47,6 +48,7 @@ struct dw_dma_slave {
		struct dw_dma_platform_data {
		unsigned int nr_channels;
		bool is_private;
		bool is_memcpy;
		#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
		#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
		unsigned char chan_allocation_order;