powerpc/85xx: Rework P1020RDB device tree (4e36afa7) · Commits · e / devices / android_kernel_samsung_exynos9810

arch/powerpc/boot/dts/fsl/p1020si-post.dtsi

0 → 100644

+174 −0

Original line number	Diff line number	Diff line
		/*
		* P1020/P1011 Silicon/SoC Device Tree Source (post include)
		*
		* Copyright 2011 Freescale Semiconductor Inc.
		*
		* Redistribution and use in source and binary forms, with or without
		* modification, are permitted provided that the following conditions are met:
		* * Redistributions of source code must retain the above copyright
		* notice, this list of conditions and the following disclaimer.
		* * Redistributions in binary form must reproduce the above copyright
		* notice, this list of conditions and the following disclaimer in the
		* documentation and/or other materials provided with the distribution.
		* * Neither the name of Freescale Semiconductor nor the
		* names of its contributors may be used to endorse or promote products
		* derived from this software without specific prior written permission.
		*
		*
		* ALTERNATIVELY, this software may be distributed under the terms of the
		* GNU General Public License ("GPL") as published by the Free Software
		* Foundation, either version 2 of that License or (at your option) any
		* later version.
		*
		* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
		* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
		* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
		* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
		* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
		* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
		* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
		* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
		* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		*/

		&lbc {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
		interrupts = <19 2 0 0>;
		};

		/* controller at 0x9000 */
		&pci0 {
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#size-cells = <2>;
		#address-cells = <3>;
		bus-range = <0 255>;
		clock-frequency = <33333333>;
		interrupts = <16 2 0 0>;

		pcie@0 {
		reg = <0 0 0 0 0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";
		interrupts = <16 2 0 0>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
		/* IDSEL 0x0 */
		0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
		0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
		0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
		0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
		>;
		};
		};

		/* controller at 0xa000 */
		&pci1 {
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#size-cells = <2>;
		#address-cells = <3>;
		bus-range = <0 255>;
		clock-frequency = <33333333>;
		interrupts = <16 2 0 0>;

		pcie@0 {
		reg = <0 0 0 0 0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";
		interrupts = <16 2 0 0>;
		interrupt-map-mask = <0xf800 0 0 7>;

		interrupt-map = <
		/* IDSEL 0x0 */
		0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
		0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
		0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
		0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
		>;
		};
		};

		&soc {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "fsl,p1020-immr", "simple-bus";
		bus-frequency = <0>; // Filled out by uboot.

		ecm-law@0 {
		compatible = "fsl,ecm-law";
		reg = <0x0 0x1000>;
		fsl,num-laws = <12>;
		};

		ecm@1000 {
		compatible = "fsl,p1020-ecm", "fsl,ecm";
		reg = <0x1000 0x1000>;
		interrupts = <16 2 0 0>;
		};

		memory-controller@2000 {
		compatible = "fsl,p1020-memory-controller";
		reg = <0x2000 0x1000>;
		interrupts = <16 2 0 0>;
		};

		/include/ "pq3-i2c-0.dtsi"
		/include/ "pq3-i2c-1.dtsi"
		/include/ "pq3-duart-0.dtsi"

		/include/ "pq3-espi-0.dtsi"
		spi@7000 {
		fsl,espi-num-chipselects = <4>;
		};

		/include/ "pq3-gpio-0.dtsi"

		L2: l2-cache-controller@20000 {
		compatible = "fsl,p1020-l2-cache-controller";
		reg = <0x20000 0x1000>;
		cache-line-size = <32>; // 32 bytes
		cache-size = <0x40000>; // L2,256K
		interrupts = <16 2 0 0>;
		};

		/include/ "pq3-dma-0.dtsi"
		/include/ "pq3-usb2-dr-0.dtsi"
		/include/ "pq3-usb2-dr-1.dtsi"

		/include/ "pq3-esdhc-0.dtsi"
		/include/ "pq3-sec3.3-0.dtsi"

		/include/ "pq3-mpic.dtsi"
		/include/ "pq3-mpic-timer-B.dtsi"

		/include/ "pq3-etsec2-0.dtsi"
		enet0: enet0_grp2: ethernet@b0000 {
		};

		/include/ "pq3-etsec2-1.dtsi"
		enet1: enet1_grp2: ethernet@b1000 {
		};

		/include/ "pq3-etsec2-2.dtsi"
		enet2: enet2_grp2: ethernet@b2000 {
		};

		global-utilities@e0000 {
		compatible = "fsl,p1020-guts";
		reg = <0xe0000 0x1000>;
		fsl,has-rstcr;
		};
		};

		/include/ "pq3-etsec2-grp2-0.dtsi"
		/include/ "pq3-etsec2-grp2-1.dtsi"
		/include/ "pq3-etsec2-grp2-2.dtsi"

arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi

0 → 100644

+68 −0

Original line number	Diff line number	Diff line
		/*
		* P1020/P1011 Silicon/SoC Device Tree Source (pre include)
		*
		* Copyright 2011 Freescale Semiconductor Inc.
		*
		* Redistribution and use in source and binary forms, with or without
		* modification, are permitted provided that the following conditions are met:
		* * Redistributions of source code must retain the above copyright
		* notice, this list of conditions and the following disclaimer.
		* * Redistributions in binary form must reproduce the above copyright
		* notice, this list of conditions and the following disclaimer in the
		* documentation and/or other materials provided with the distribution.
		* * Neither the name of Freescale Semiconductor nor the
		* names of its contributors may be used to endorse or promote products
		* derived from this software without specific prior written permission.
		*
		*
		* ALTERNATIVELY, this software may be distributed under the terms of the
		* GNU General Public License ("GPL") as published by the Free Software
		* Foundation, either version 2 of that License or (at your option) any
		* later version.
		*
		* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
		* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
		* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
		* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
		* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
		* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
		* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
		* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
		* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		*/

		/dts-v1/;
		/ {
		compatible = "fsl,P1020";
		#address-cells = <2>;
		#size-cells = <2>;
		interrupt-parent = <&mpic>;

		aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		pci0 = &pci0;
		pci1 = &pci1;
		};

		cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,P1020@0 {
		device_type = "cpu";
		reg = <0x0>;
		next-level-cache = <&L2>;
		};

		PowerPC,P1020@1 {
		device_type = "cpu";
		reg = <0x1>;
		next-level-cache = <&L2>;
		};
		};
		};

arch/powerpc/boot/dts/p1020rdb.dts

+8 −224

Original line number	Diff line number	Diff line
		@@ -9,245 +9,26 @@
		* option) any later version.
		*/

		/include/ "p1020si.dtsi"

		/include/ "fsl/p1020si-pre.dtsi"
		/ {
		model = "fsl,P1020RDB";
		compatible = "fsl,P1020RDB";

		aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		pci0 = &pci0;
		pci1 = &pci1;
		};

		memory {
		device_type = "memory";
		};

		localbus@ffe05000 {
		board_lbc: lbc: localbus@ffe05000 {
		reg = <0 0xffe05000 0 0x1000>;

		/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
		ranges = <0x0 0x0 0x0 0xef000000 0x01000000
		0x1 0x0 0x0 0xffa00000 0x00040000
		0x2 0x0 0x0 0xffb00000 0x00020000>;

		nor@0,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "cfi-flash";
		reg = <0x0 0x0 0x1000000>;
		bank-width = <2>;
		device-width = <1>;

		partition@0 {
		/* This location must not be altered */
		/* 256KB for Vitesse 7385 Switch firmware */
		reg = <0x0 0x00040000>;
		label = "NOR (RO) Vitesse-7385 Firmware";
		read-only;
		};

		partition@40000 {
		/* 256KB for DTB Image */
		reg = <0x00040000 0x00040000>;
		label = "NOR (RO) DTB Image";
		read-only;
		};

		partition@80000 {
		/* 3.5 MB for Linux Kernel Image */
		reg = <0x00080000 0x00380000>;
		label = "NOR (RO) Linux Kernel Image";
		read-only;
		};

		partition@400000 {
		/* 11MB for JFFS2 based Root file System */
		reg = <0x00400000 0x00b00000>;
		label = "NOR (RW) JFFS2 Root File System";
		};

		partition@f00000 {
		/* This location must not be altered */
		/* 512KB for u-boot Bootloader Image */
		/* 512KB for u-boot Environment Variables */
		reg = <0x00f00000 0x00100000>;
		label = "NOR (RO) U-Boot Image";
		read-only;
		};
		};

		nand@1,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,p1020-fcm-nand",
		"fsl,elbc-fcm-nand";
		reg = <0x1 0x0 0x40000>;

		partition@0 {
		/* This location must not be altered */
		/* 1MB for u-boot Bootloader Image */
		reg = <0x0 0x00100000>;
		label = "NAND (RO) U-Boot Image";
		read-only;
		};

		partition@100000 {
		/* 1MB for DTB Image */
		reg = <0x00100000 0x00100000>;
		label = "NAND (RO) DTB Image";
		read-only;
		};

		partition@200000 {
		/* 4MB for Linux Kernel Image */
		reg = <0x00200000 0x00400000>;
		label = "NAND (RO) Linux Kernel Image";
		read-only;
		};

		partition@600000 {
		/* 4MB for Compressed Root file System Image */
		reg = <0x00600000 0x00400000>;
		label = "NAND (RO) Compressed RFS Image";
		read-only;
		};

		partition@a00000 {
		/* 7MB for JFFS2 based Root file System */
		reg = <0x00a00000 0x00700000>;
		label = "NAND (RW) JFFS2 Root File System";
		};

		partition@1100000 {
		/* 15MB for JFFS2 based Root file System */
		reg = <0x01100000 0x00f00000>;
		label = "NAND (RW) Writable User area";
		};
		};

		L2switch@2,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "vitesse-7385";
		reg = <0x2 0x0 0x20000>;
		};

		};

		soc@ffe00000 {
		i2c@3000 {
		rtc@68 {
		compatible = "dallas,ds1339";
		reg = <0x68>;
		};
		};

		spi@7000 {
		flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "spansion,s25sl12801";
		reg = <0>;
		spi-max-frequency = <40000000>; /* input clock */

		partition@u-boot {
		/* 512KB for u-boot Bootloader Image */
		reg = <0x0 0x00080000>;
		label = "u-boot";
		read-only;
		};

		partition@dtb {
		/* 512KB for DTB Image */
		reg = <0x00080000 0x00080000>;
		label = "dtb";
		read-only;
		};

		partition@kernel {
		/* 4MB for Linux Kernel Image */
		reg = <0x00100000 0x00400000>;
		label = "kernel";
		read-only;
		};

		partition@fs {
		/* 4MB for Compressed RFS Image */
		reg = <0x00500000 0x00400000>;
		label = "file system";
		read-only;
		};

		partition@jffs-fs {
		/* 7MB for JFFS2 based RFS */
		reg = <0x00900000 0x00700000>;
		label = "file system jffs2";
		};
		};
		};

		mdio@24000 {

		phy0: ethernet-phy@0 {
		interrupt-parent = <&mpic>;
		interrupts = <3 1>;
		reg = <0x0>;
		};

		phy1: ethernet-phy@1 {
		interrupt-parent = <&mpic>;
		interrupts = <2 1>;
		reg = <0x1>;
		};
		};

		mdio@25000 {

		tbi0: tbi-phy@11 {
		reg = <0x11>;
		device_type = "tbi-phy";
		};
		};

		enet0: ethernet@b0000 {
		fixed-link = <1 1 1000 0 0>;
		phy-connection-type = "rgmii-id";

		};

		enet1: ethernet@b1000 {
		phy-handle = <&phy0>;
		tbi-handle = <&tbi0>;
		phy-connection-type = "sgmii";

		};

		enet2: ethernet@b2000 {
		phy-handle = <&phy1>;
		phy-connection-type = "rgmii-id";

		};

		usb@22000 {
		phy_type = "ulpi";
		};

		/* USB2 is shared with localbus, so it must be disabled
		by default. We can't put 'status = "disabled";' here
		since U-Boot doesn't clear the status property when
		it enables USB2. OTOH, U-Boot does create a new node
		when there isn't any. So, just comment it out.
		usb@23000 {
		phy_type = "ulpi";
		};
		*/

		board_soc: soc: soc@ffe00000 {
		ranges = <0x0 0x0 0xffe00000 0x100000>;
		};

		pci0: pcie@ffe09000 {
		@@ -280,3 +61,6 @@
		};
		};
		};

		/include/ "p1020rdb.dtsi"
		/include/ "fsl/p1020si-post.dtsi"

arch/powerpc/boot/dts/p1020rdb.dtsi

0 → 100644

+242 −0

Original line number	Diff line number	Diff line
		/*
		* P1020 RDB Device Tree Source stub (no addresses or top-level ranges)
		*
		* Copyright 2011 Freescale Semiconductor Inc.
		*
		* Redistribution and use in source and binary forms, with or without
		* modification, are permitted provided that the following conditions are met:
		* * Redistributions of source code must retain the above copyright
		* notice, this list of conditions and the following disclaimer.
		* * Redistributions in binary form must reproduce the above copyright
		* notice, this list of conditions and the following disclaimer in the
		* documentation and/or other materials provided with the distribution.
		* * Neither the name of Freescale Semiconductor nor the
		* names of its contributors may be used to endorse or promote products
		* derived from this software without specific prior written permission.
		*
		*
		* ALTERNATIVELY, this software may be distributed under the terms of the
		* GNU General Public License ("GPL") as published by the Free Software
		* Foundation, either version 2 of that License or (at your option) any
		* later version.
		*
		* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
		* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
		* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
		* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
		* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
		* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
		* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
		* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
		* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		*/

		&board_lbc {
		nor@0,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "cfi-flash";
		reg = <0x0 0x0 0x1000000>;
		bank-width = <2>;
		device-width = <1>;

		partition@0 {
		/* This location must not be altered */
		/* 256KB for Vitesse 7385 Switch firmware */
		reg = <0x0 0x00040000>;
		label = "NOR (RO) Vitesse-7385 Firmware";
		read-only;
		};

		partition@40000 {
		/* 256KB for DTB Image */
		reg = <0x00040000 0x00040000>;
		label = "NOR (RO) DTB Image";
		read-only;
		};

		partition@80000 {
		/* 3.5 MB for Linux Kernel Image */
		reg = <0x00080000 0x00380000>;
		label = "NOR (RO) Linux Kernel Image";
		read-only;
		};

		partition@400000 {
		/* 11MB for JFFS2 based Root file System */
		reg = <0x00400000 0x00b00000>;
		label = "NOR (RW) JFFS2 Root File System";
		};

		partition@f00000 {
		/* This location must not be altered */
		/* 512KB for u-boot Bootloader Image */
		/* 512KB for u-boot Environment Variables */
		reg = <0x00f00000 0x00100000>;
		label = "NOR (RO) U-Boot Image";
		read-only;
		};
		};

		nand@1,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,p1020-fcm-nand",
		"fsl,elbc-fcm-nand";
		reg = <0x1 0x0 0x40000>;

		partition@0 {
		/* This location must not be altered */
		/* 1MB for u-boot Bootloader Image */
		reg = <0x0 0x00100000>;
		label = "NAND (RO) U-Boot Image";
		read-only;
		};

		partition@100000 {
		/* 1MB for DTB Image */
		reg = <0x00100000 0x00100000>;
		label = "NAND (RO) DTB Image";
		read-only;
		};

		partition@200000 {
		/* 4MB for Linux Kernel Image */
		reg = <0x00200000 0x00400000>;
		label = "NAND (RO) Linux Kernel Image";
		read-only;
		};

		partition@600000 {
		/* 4MB for Compressed Root file System Image */
		reg = <0x00600000 0x00400000>;
		label = "NAND (RO) Compressed RFS Image";
		read-only;
		};

		partition@a00000 {
		/* 7MB for JFFS2 based Root file System */
		reg = <0x00a00000 0x00700000>;
		label = "NAND (RW) JFFS2 Root File System";
		};

		partition@1100000 {
		/* 15MB for JFFS2 based Root file System */
		reg = <0x01100000 0x00f00000>;
		label = "NAND (RW) Writable User area";
		};
		};

		L2switch@2,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "vitesse-7385";
		reg = <0x2 0x0 0x20000>;
		};
		};

		&board_soc {
		i2c@3000 {
		rtc@68 {
		compatible = "dallas,ds1339";
		reg = <0x68>;
		};
		};

		spi@7000 {
		flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "spansion,s25sl12801";
		reg = <0>;
		spi-max-frequency = <40000000>; /* input clock */

		partition@u-boot {
		/* 512KB for u-boot Bootloader Image */
		reg = <0x0 0x00080000>;
		label = "u-boot";
		read-only;
		};

		partition@dtb {
		/* 512KB for DTB Image */
		reg = <0x00080000 0x00080000>;
		label = "dtb";
		read-only;
		};

		partition@kernel {
		/* 4MB for Linux Kernel Image */
		reg = <0x00100000 0x00400000>;
		label = "kernel";
		read-only;
		};

		partition@fs {
		/* 4MB for Compressed RFS Image */
		reg = <0x00500000 0x00400000>;
		label = "file system";
		read-only;
		};

		partition@jffs-fs {
		/* 7MB for JFFS2 based RFS */
		reg = <0x00900000 0x00700000>;
		label = "file system jffs2";
		};
		};
		};

		usb@22000 {
		phy_type = "ulpi";
		};

		/* USB2 is shared with localbus, so it must be disabled
		by default. We can't put 'status = "disabled";' here
		since U-Boot doesn't clear the status property when
		it enables USB2. OTOH, U-Boot does create a new node
		when there isn't any. So, just comment it out.
		usb@23000 {
		phy_type = "ulpi";
		};
		*/

		mdio@24000 {
		phy0: ethernet-phy@0 {
		interrupt-parent = <&mpic>;
		interrupts = <3 1>;
		reg = <0x0>;
		};

		phy1: ethernet-phy@1 {
		interrupt-parent = <&mpic>;
		interrupts = <2 1>;
		reg = <0x1>;
		};
		};

		mdio@25000 {
		tbi0: tbi-phy@11 {
		reg = <0x11>;
		device_type = "tbi-phy";
		};
		};

		enet0: ethernet@b0000 {
		fixed-link = <1 1 1000 0 0>;
		phy-connection-type = "rgmii-id";

		};

		enet1: ethernet@b1000 {
		phy-handle = <&phy0>;
		tbi-handle = <&tbi0>;
		phy-connection-type = "sgmii";
		};

		enet2: ethernet@b2000 {
		phy-handle = <&phy1>;
		phy-connection-type = "rgmii-id";
		};
		};

arch/powerpc/boot/dts/p1020si.dtsi

deleted100644 → 0

+0 −407

File deleted.

Preview size limit exceeded, changes collapsed.