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Commit 3533bf6b authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
Browse files

ath9k: Fix regulatory compliance



To comply with ETSI regulations, make sure that
the CCA registers are programmed with the threshold
values from the EEPROM/Caldata. A new field is used
to indicate if the card has been calibrated with the
required threshold information.

Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent ee65b388
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+32 −0
Original line number Diff line number Diff line
@@ -4121,6 +4121,37 @@ static void ar9003_hw_thermo_cal_apply(struct ath_hw *ah)
	}
}

static void ar9003_hw_apply_minccapwr_thresh(struct ath_hw *ah,
					     bool is2ghz)
{
	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
	const u_int32_t cca_ctrl[AR9300_MAX_CHAINS] = {
		AR_PHY_CCA_CTRL_0,
		AR_PHY_CCA_CTRL_1,
		AR_PHY_CCA_CTRL_2,
	};
	int chain;
	u32 val;

	if (is2ghz) {
		if (!(eep->base_ext1.misc_enable & BIT(2)))
			return;
	} else {
		if (!(eep->base_ext1.misc_enable & BIT(3)))
			return;
	}

	for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
		if (!(ah->caps.tx_chainmask & BIT(chain)))
			continue;

		val = ar9003_modal_header(ah, is2ghz)->noiseFloorThreshCh[chain];
		REG_RMW_FIELD(ah, cca_ctrl[chain],
			      AR_PHY_EXT_CCA0_THRESH62_1, val);
	}

}

static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
					     struct ath9k_channel *chan)
{
@@ -4135,6 +4166,7 @@ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
	if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
		ar9003_hw_internal_regulator_apply(ah);
	ar9003_hw_apply_tuning_caps(ah);
	ar9003_hw_apply_minccapwr_thresh(ah, chan);
	ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
	ar9003_hw_thermometer_apply(ah);
	ar9003_hw_thermo_cal_apply(ah);
+3 −1
Original line number Diff line number Diff line
@@ -270,7 +270,7 @@
#define AR_PHY_AGC              (AR_AGC_BASE + 0x14)
#define AR_PHY_EXT_ATTEN_CTL_0  (AR_AGC_BASE + 0x18)
#define AR_PHY_CCA_0            (AR_AGC_BASE + 0x1c)
#define AR_PHY_EXT_CCA0         (AR_AGC_BASE + 0x20)
#define AR_PHY_CCA_CTRL_0       (AR_AGC_BASE + 0x20)
#define AR_PHY_RESTART          (AR_AGC_BASE + 0x24)

/*
@@ -398,6 +398,8 @@
#define AR9280_PHY_CCA_THRESH62_S   12
#define AR_PHY_EXT_CCA0_THRESH62    0x000000FF
#define AR_PHY_EXT_CCA0_THRESH62_S  0
#define AR_PHY_EXT_CCA0_THRESH62_1    0x000001FF
#define AR_PHY_EXT_CCA0_THRESH62_1_S  0
#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK          0x0000003F
#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S        0
#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME           0x00001FC0