Commit 25a56705 authored Mar 16, 2016 by Dongwon Kim Committed by Imre Deak Apr 11, 2016

drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit



For BXT, description of polarities of PORT_PLL_REF_SEL
has been reversed for newer Gen9LP steppings according to the
recent update in Bspec. This bit now should be set for
"Non-SSC" mode for all Gen9LP starting from B0 stepping.

v2: Only B0 and newer stepping should be affected by this
change.

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94866


Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1458176773-26925-1-git-send-email-dongwon.kim@intel.com

parent c0ead703

drivers/gpu/drm/i915/intel_dpll_mgr.c

+9 −1

Original line number	Diff line number	Diff line
		@@ -1296,7 +1296,15 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
		enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */

		temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
		/*
		* Definition of each bit polarity has been changed
		* after A1 stepping
		*/
		if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
		temp &= ~PORT_PLL_REF_SEL;
		else
		temp \|= PORT_PLL_REF_SEL;

		/* Non-SSC reference */
		I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);