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Commit 16e11b99 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Ville Syrjälä
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drm/i915/bxt: Expose DC5 entry count 



For bxt CSR firmware exposes a count of dc5 entries. Expose
it through debugs

Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Tested-by: Daniel Stone <daniels@collabora.com> # SKL
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
parent 8337206d

drivers/gpu/drm/i915/i915_debugfs.c

+3 −0
Original line number Diff line number Diff line
@@ -2818,6 +2818,9 @@ static int i915_dmc_info(struct seq_file *m, void *unused) 
			   I915_READ(SKL_CSR_DC3_DC5_COUNT));

		seq_printf(m, "DC5 -> DC6 count: %d\n",

			   I915_READ(SKL_CSR_DC5_DC6_COUNT));

	} else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {

		seq_printf(m, "DC3 -> DC5 count: %d\n",

			   I915_READ(BXT_CSR_DC3_DC5_COUNT));

	}



	intel_runtime_pm_put(dev_priv);

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -5700,6 +5700,7 @@ enum skl_disp_power_wells { 
/* DMC/CSR */

#define SKL_CSR_DC3_DC5_COUNT	0x80030

#define SKL_CSR_DC5_DC6_COUNT	0x8002C

#define BXT_CSR_DC3_DC5_COUNT	0x80038



/* interrupts */

#define DE_MASTER_IRQ_CONTROL   (1 << 31)