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Commit 109eee2f authored by Jianwei Wang's avatar Jianwei Wang
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drm/layerscape: Add Freescale DCU DRM driver



This patch add support for Two Dimensional Animation and Compositing
Engine (2D-ACE) on the Freescale SoCs.

2D-ACE is a Freescale display controller. 2D-ACE describes
the functionality of the module extremely well its name is a value
that cannot be used as a token in programming languages.
Instead the valid token "DCU" is used to tag the register names and
function names.

The Display Controller Unit (DCU) module is a system master that
fetches graphics stored in internal or external memory and displays
them on a TFT LCD panel. A wide range of panel sizes is supported
and the timing of the interface signals is highly configurable.
Graphics are read directly from memory and then blended in real-time,
which allows for dynamic content creation with minimal CPU
intervention.

The features:
(1) Full RGB888 output to TFT LCD panel.
(2) Blending of each pixel using up to 4 source layers
dependent
on size of panel.
(3) Each graphic layer can be placed with one pixel resolution
in either axis.
(4) Each graphic layer support RGB565 and RGB888 direct colors
without alpha channel and BGRA8888 BGRA4444 ARGB1555 direct
colors
with an alpha channel and YUV422 format.
(5) Each graphic layer support alpha blending with 8-bit
resolution.
This is a simplified version, only one primary plane, one
framebuffer, one crtc, one connector and one encoder for TFT
LCD panel.

Signed-off-by: default avatarAlison Wang <b18965@freescale.com>
Signed-off-by: default avatarXiubo Li <lixiubo@cmss.chinamobile.com>
Signed-off-by: default avatarJianwei Wang <jianwei.wang.chn@gmail.com>
Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 294947a5
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+22 −0
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Device Tree bindings for Freescale DCU DRM Driver

Required properties:
- compatible:		Should be one of
	* "fsl,ls1021a-dcu".
	* "fsl,vf610-dcu".

- reg:			Address and length of the register set for dcu.
- clocks:		From common clock binding: handle to dcu clock.
- clock-names:		From common clock binding: Shall be "dcu".
- big-endian		Boolean property, LS1021A DCU registers are big-endian.
- fsl,panel:		The phandle to panel node.

Examples:
dcu: dcu@2ce0000 {
	compatible = "fsl,ls1021a-dcu";
	reg = <0x0 0x2ce0000 0x0 0x10000>;
	clocks = <&platform_clk 0>;
	clock-names = "dcu";
	big-endian;
	fsl,panel = <&panel>;
};
+2 −0
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@@ -249,6 +249,8 @@ source "drivers/gpu/drm/virtio/Kconfig"

source "drivers/gpu/drm/msm/Kconfig"

source "drivers/gpu/drm/fsl-dcu/Kconfig"

source "drivers/gpu/drm/tegra/Kconfig"

source "drivers/gpu/drm/panel/Kconfig"
+1 −0
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@@ -70,3 +70,4 @@ obj-$(CONFIG_DRM_IMX) += imx/
obj-y			+= i2c/
obj-y			+= panel/
obj-y			+= bridge/
obj-$(CONFIG_DRM_FSL_DCU) += fsl-dcu/
+18 −0
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config DRM_FSL_DCU
	tristate "DRM Support for Freescale DCU"
	depends on DRM && OF && ARM
	select BACKLIGHT_CLASS_DEVICE
	select BACKLIGHT_LCD_SUPPORT
	select DRM_KMS_HELPER
	select DRM_KMS_CMA_HELPER
	select DRM_KMS_FB_HELPER
	select DRM_PANEL
	select FB_SYS_FILLRECT
	select FB_SYS_COPYAREA
	select FB_SYS_IMAGEBLIT
	select FB_SYS_FOPS
	select REGMAP_MMIO
	select VIDEOMODE_HELPERS
	help
	  Choose this option if you have an Freescale DCU chipset.
	  If M is selected the module will be called fsl-dcu-drm.
+7 −0
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fsl-dcu-drm-y := fsl_dcu_drm_drv.o \
		 fsl_dcu_drm_kms.o \
		 fsl_dcu_drm_rgb.o \
		 fsl_dcu_drm_plane.o \
		 fsl_dcu_drm_crtc.o \
		 fsl_dcu_drm_fbdev.o
obj-$(CONFIG_DRM_FSL_DCU)	+= fsl-dcu-drm.o
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