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Commit 05135b4c authored by Mike Turquette's avatar Mike Turquette
Browse files

Merge tag 'clk-mvebu-3xx-3.15' of git://git.infradead.org/linux-mvebu into clk-next-mvebu 

clock: mvebu new SoC changes for v3.15

 - mvebu (Armada 375/380/385)
    - extend corediv clock driver to support new SoCs
    - add core and gating clock drivers for new SoCs
parents c112c1d8 e9646fe1

Documentation/devicetree/bindings/clock/mvebu-core-clock.txt

+14 −0
Original line number Diff line number Diff line
@@ -11,6 +11,18 @@ The following is a list of provided IDs and clock names on Armada 370/XP: 
 3 = hclk    (DRAM control clock)

 4 = dramclk (DDR clock)



The following is a list of provided IDs and clock names on Armada 375:

 0 = tclk    (Internal Bus clock)

 1 = cpuclk  (CPU clock)

 2 = l2clk   (L2 Cache clock)

 3 = ddrclk  (DDR clock)



The following is a list of provided IDs and clock names on Armada 380/385:

 0 = tclk    (Internal Bus clock)

 1 = cpuclk  (CPU clock)

 2 = l2clk   (L2 Cache clock)

 3 = ddrclk  (DDR clock)



The following is a list of provided IDs and clock names on Kirkwood and Dove:

 0 = tclk   (Internal Bus clock)

 1 = cpuclk (CPU0 clock)
@@ -20,6 +32,8 @@ The following is a list of provided IDs and clock names on Kirkwood and Dove: 
Required properties:

- compatible : shall be one of the following:

	"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks

	"marvell,armada-375-core-clock" - For Armada 375 SoC core clocks

	"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks

	"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks

	"marvell,dove-core-clock" - for Dove SoC core clocks

	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)

Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt

+61 −4
Original line number Diff line number Diff line 
* Gated Clock bindings for Marvell EBU SoCs



Marvell Armada 370/XP, Dove and Kirkwood allow some peripheral clocks to be

gated to save some power. The clock consumer should specify the desired clock

by having the clock ID in its "clocks" phandle cell. The clock ID is directly

mapped to the corresponding clock gating control bit in HW to ease manual clock

Marvell Armada 370/375/380/385/XP, Dove and Kirkwood allow some

peripheral clocks to be gated to save some power. The clock consumer

should specify the desired clock by having the clock ID in its

"clocks" phandle cell. The clock ID is directly mapped to the

corresponding clock gating control bit in HW to ease manual clock

lookup in datasheet.



The following is a list of provided IDs for Armada 370:
@@ -22,6 +23,60 @@ ID Clock Peripheral 
28	ddr	DDR Cntrl

30	sata1	SATA Host 0



The following is a list of provided IDs for Armada 375:

ID	Clock		Peripheral

-----------------------------------

2	mu		Management Unit

3	pp		Packet Processor

4	ptp		PTP

5	pex0		PCIe 0 Clock out

6	pex1		PCIe 1 Clock out

8	audio		Audio Cntrl

11	nd_clk		Nand Flash Cntrl

14	sata0_link	SATA 0 Link

15	sata0_core	SATA 0 Core

16	usb3		USB3 Host

17	sdio		SDHCI Host

18	usb		USB Host

19	gop		Gigabit Ethernet MAC

20	sata1_link	SATA 1 Link

21	sata1_core	SATA 1 Core

22	xor0		XOR DMA 0

23	xor1		XOR DMA 0

24	copro		Coprocessor

25	tdm		Time Division Mplx

28	crypto0_enc	Cryptographic Unit Port 0 Encryption

29	crypto0_core	Cryptographic Unit Port 0 Core

30	crypto1_enc	Cryptographic Unit Port 1 Encryption

31	crypto1_core	Cryptographic Unit Port 1 Core



The following is a list of provided IDs for Armada 380/385:

ID	Clock		Peripheral

-----------------------------------

0	audio		Audio

2	ge2		Gigabit Ethernet 2

3	ge1		Gigabit Ethernet 1

4	ge0		Gigabit Ethernet 0

5	pex1		PCIe 1

6	pex2		PCIe 2

7	pex3		PCIe 3

8	pex0		PCIe 0

9	usb3h0		USB3 Host 0

10	usb3h1		USB3 Host 1

11	usb3d		USB3 Device

13	bm		Buffer Management

14	crypto0z	Cryptographic 0 Z

15	sata0		SATA 0

16	crypto1z	Cryptographic 1 Z

17	sdio		SDIO

18	usb2		USB 2

21	crypto1		Cryptographic 1

22	xor0		XOR 0

23	crypto0		Cryptographic 0

25	tdm		Time Division Multiplexing

28	xor1		XOR 1

30	sata1		SATA 1



The following is a list of provided IDs for Armada XP:

ID	Clock	Peripheral

-----------------------------------
@@ -95,6 +150,8 @@ ID Clock Peripheral 
Required properties:

- compatible : shall be one of the following:

	"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating

	"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating

	"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating

	"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating

	"marvell,dove-gating-clock" - for Dove SoC clock gating

	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating

drivers/clk/mvebu/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -13,6 +13,14 @@ config ARMADA_370_CLK 
	select MVEBU_CLK_CPU

	select MVEBU_CLK_COREDIV



config ARMADA_375_CLK

	bool

	select MVEBU_CLK_COMMON



config ARMADA_38X_CLK

	bool

	select MVEBU_CLK_COMMON



config ARMADA_XP_CLK

	bool

	select MVEBU_CLK_COMMON

drivers/clk/mvebu/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -3,6 +3,8 @@ obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o 
obj-$(CONFIG_MVEBU_CLK_COREDIV)	+= clk-corediv.o



obj-$(CONFIG_ARMADA_370_CLK)	+= armada-370.o

obj-$(CONFIG_ARMADA_375_CLK)	+= armada-375.o

obj-$(CONFIG_ARMADA_38X_CLK)	+= armada-38x.o

obj-$(CONFIG_ARMADA_XP_CLK)	+= armada-xp.o

obj-$(CONFIG_DOVE_CLK)		+= dove.o

obj-$(CONFIG_KIRKWOOD_CLK)	+= kirkwood.o

drivers/clk/mvebu/armada-375.c

0 → 100644
+184 −0
Original line number Diff line number Diff line 
/*

 * Marvell Armada 375 SoC clocks

 *

 * Copyright (C) 2014 Marvell

 *

 * Gregory CLEMENT <gregory.clement@free-electrons.com>

 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

 * Andrew Lunn <andrew@lunn.ch>

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2.  This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */



#include <linux/kernel.h>

#include <linux/clk-provider.h>

#include <linux/io.h>

#include <linux/of.h>

#include "common.h"



/*

 * Core Clocks

 */



/*

 * For the Armada 375 SoCs, the CPU, DDR and L2 clocks frequencies are

 * all modified at the same time, and not separately as for the Armada

 * 370 or the Armada XP SoCs.

 *

 * SAR0[21:17]   : CPU frequency    DDR frequency   L2 frequency

 *		 6   =  400 MHz	    400 MHz	    200 MHz

 *		 15  =  600 MHz	    600 MHz	    300 MHz

 *		 21  =  800 MHz	    534 MHz	    400 MHz

 *		 25  = 1000 MHz	    500 MHz	    500 MHz

 *		 others reserved.

 *

 * SAR0[22]   : TCLK frequency

 *		 0 = 166 MHz

 *		 1 = 200 MHz

 */



#define SAR1_A375_TCLK_FREQ_OPT		   22

#define SAR1_A375_TCLK_FREQ_OPT_MASK	   0x1

#define SAR1_A375_CPU_DDR_L2_FREQ_OPT	   17

#define SAR1_A375_CPU_DDR_L2_FREQ_OPT_MASK 0x1F



static const u32 armada_375_tclk_frequencies[] __initconst = {

	166000000,

	200000000,

};



static u32 __init armada_375_get_tclk_freq(void __iomem *sar)

{

	u8 tclk_freq_select;



	tclk_freq_select = ((readl(sar) >> SAR1_A375_TCLK_FREQ_OPT) &

			    SAR1_A375_TCLK_FREQ_OPT_MASK);

	return armada_375_tclk_frequencies[tclk_freq_select];

}





static const u32 armada_375_cpu_frequencies[] __initconst = {

	0, 0, 0, 0, 0, 0,

	400000000,

	0, 0, 0, 0, 0, 0, 0, 0,

	600000000,

	0, 0, 0, 0, 0,

	800000000,

	0, 0, 0,

	1000000000,

};



static u32 __init armada_375_get_cpu_freq(void __iomem *sar)

{

	u8 cpu_freq_select;



	cpu_freq_select = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) &

			   SAR1_A375_CPU_DDR_L2_FREQ_OPT_MASK);

	if (cpu_freq_select >= ARRAY_SIZE(armada_375_cpu_frequencies)) {

		pr_err("Selected CPU frequency (%d) unsupported\n",

			cpu_freq_select);

		return 0;

	} else

		return armada_375_cpu_frequencies[cpu_freq_select];

}



enum { A375_CPU_TO_DDR, A375_CPU_TO_L2 };



static const struct coreclk_ratio armada_375_coreclk_ratios[] __initconst = {

	{ .id = A375_CPU_TO_L2,	 .name = "l2clk" },

	{ .id = A375_CPU_TO_DDR, .name = "ddrclk" },

};



static const int armada_375_cpu_l2_ratios[32][2] __initconst = {

	{0, 1}, {0, 1}, {0, 1}, {0, 1},

	{0, 1}, {0, 1}, {1, 2}, {0, 1},

	{0, 1}, {0, 1}, {0, 1}, {0, 1},

	{0, 1}, {0, 1}, {0, 1}, {1, 2},

	{0, 1}, {0, 1}, {0, 1}, {0, 1},

	{0, 1}, {1, 2}, {0, 1}, {0, 1},

	{0, 1}, {1, 2}, {0, 1}, {0, 1},

	{0, 1}, {0, 1}, {0, 1}, {0, 1},

};



static const int armada_375_cpu_ddr_ratios[32][2] __initconst = {

	{0, 1}, {0, 1}, {0, 1}, {0, 1},

	{0, 1}, {0, 1}, {1, 1}, {0, 1},

	{0, 1}, {0, 1}, {0, 1}, {0, 1},

	{0, 1}, {0, 1}, {0, 1}, {2, 3},

	{0, 1}, {0, 1}, {0, 1}, {0, 1},

	{0, 1}, {2, 3}, {0, 1}, {0, 1},

	{0, 1}, {1, 2}, {0, 1}, {0, 1},

	{0, 1}, {0, 1}, {0, 1}, {0, 1},

};



static void __init armada_375_get_clk_ratio(

	void __iomem *sar, int id, int *mult, int *div)

{

	u32 opt = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) &

		SAR1_A375_CPU_DDR_L2_FREQ_OPT_MASK);



	switch (id) {

	case A375_CPU_TO_L2:

		*mult = armada_375_cpu_l2_ratios[opt][0];

		*div = armada_375_cpu_l2_ratios[opt][1];

		break;

	case A375_CPU_TO_DDR:

		*mult = armada_375_cpu_ddr_ratios[opt][0];

		*div = armada_375_cpu_ddr_ratios[opt][1];

		break;

	}

}



static const struct coreclk_soc_desc armada_375_coreclks = {

	.get_tclk_freq = armada_375_get_tclk_freq,

	.get_cpu_freq = armada_375_get_cpu_freq,

	.get_clk_ratio = armada_375_get_clk_ratio,

	.ratios = armada_375_coreclk_ratios,

	.num_ratios = ARRAY_SIZE(armada_375_coreclk_ratios),

};



static void __init armada_375_coreclk_init(struct device_node *np)

{

	mvebu_coreclk_setup(np, &armada_375_coreclks);

}

CLK_OF_DECLARE(armada_375_core_clk, "marvell,armada-375-core-clock",

	       armada_375_coreclk_init);



/*

 * Clock Gating Control

 */

static const struct clk_gating_soc_desc armada_375_gating_desc[] __initconst = {

	{ "mu", NULL, 2 },

	{ "pp", NULL, 3 },

	{ "ptp", NULL, 4 },

	{ "pex0", NULL, 5 },

	{ "pex1", NULL, 6 },

	{ "audio", NULL, 8 },

	{ "nd_clk", "nand", 11 },

	{ "sata0_link", "sata0_core", 14 },

	{ "sata0_core", NULL, 15 },

	{ "usb3", NULL, 16 },

	{ "sdio", NULL, 17 },

	{ "usb", NULL, 18 },

	{ "gop", NULL, 19 },

	{ "sata1_link", "sata1_core", 20 },

	{ "sata1_core", NULL, 21 },

	{ "xor0", NULL, 22 },

	{ "xor1", NULL, 23 },

	{ "copro", NULL, 24 },

	{ "tdm", NULL, 25 },

	{ "crypto0_enc", NULL, 28 },

	{ "crypto0_core", NULL, 29 },

	{ "crypto1_enc", NULL, 30 },

	{ "crypto1_core", NULL, 31 },

	{ }

};



static void __init armada_375_clk_gating_init(struct device_node *np)

{

	mvebu_clk_gating_setup(np, armada_375_gating_desc);

}

CLK_OF_DECLARE(armada_375_clk_gating, "marvell,armada-375-gating-clock",

	       armada_375_clk_gating_init);