enic: add Cisco 10G Ethernet NIC driver

W:	http://www.ibm.com/developerworks/power/cell/

S:	Supported

CISCO 10G ETHERNET DRIVER

P:	Scott Feldman

M:	scofeldm@cisco.com

P:	Joe Eykholt

M:	jeykholt@cisco.com

S:	Supported

CFAG12864B LCD DRIVER

P:	Miguel Ojeda Sandonis

M:	miguel.ojeda.sandonis@gmail.com

	  To compile the driver as a module, choose M here. The module

	  will be called ehea.

config ENIC

	tristate "E, the Cisco 10G Ethernet NIC"

	depends on PCI && INET

	select INET_LRO

	help

	  This enables the support for the Cisco 10G Ethernet card.

config IXGBE

	tristate "Intel(R) 10GbE PCI Express adapters support"

	depends on PCI && INET

obj-$(CONFIG_ATL1E) += atl1e/

obj-$(CONFIG_GIANFAR) += gianfar_driver.o

obj-$(CONFIG_TEHUTI) += tehuti.o

obj-$(CONFIG_ENIC) += enic/

gianfar_driver-objs := gianfar.o \

		gianfar_ethtool.o \

obj-$(CONFIG_ENIC) := enic.o

enic-y := enic_main.o vnic_cq.o vnic_intr.o vnic_wq.o \

	enic_res.o vnic_dev.o vnic_rq.o

/*

 * Copyright 2008 Cisco Systems, Inc.  All rights reserved.

 * Copyright 2007 Nuova Systems, Inc.  All rights reserved.

 *

 * This program is free software; you may redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; version 2 of the License.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

 * SOFTWARE.

 *

 */

#ifndef _CQ_DESC_H_

#define _CQ_DESC_H_

/*

 * Completion queue descriptor types

 */

enum cq_desc_types {

	CQ_DESC_TYPE_WQ_ENET = 0,

	CQ_DESC_TYPE_DESC_COPY = 1,

	CQ_DESC_TYPE_WQ_EXCH = 2,

	CQ_DESC_TYPE_RQ_ENET = 3,

	CQ_DESC_TYPE_RQ_FCP = 4,

};

/* Completion queue descriptor: 16B

 *

 * All completion queues have this basic layout.  The

 * type_specfic area is unique for each completion

 * queue type.

 */

struct cq_desc {

	__le16 completed_index;

	__le16 q_number;

	u8 type_specfic[11];

	u8 type_color;

};

#define CQ_DESC_TYPE_BITS        7

#define CQ_DESC_TYPE_MASK        ((1 << CQ_DESC_TYPE_BITS) - 1)

#define CQ_DESC_COLOR_MASK       1

#define CQ_DESC_Q_NUM_BITS       10

#define CQ_DESC_Q_NUM_MASK       ((1 << CQ_DESC_Q_NUM_BITS) - 1)

#define CQ_DESC_COMP_NDX_BITS    12

#define CQ_DESC_COMP_NDX_MASK    ((1 << CQ_DESC_COMP_NDX_BITS) - 1)

static inline void cq_desc_dec(const struct cq_desc *desc_arg,

	u8 *type, u8 *color, u16 *q_number, u16 *completed_index)

{

	const struct cq_desc *desc = desc_arg;

	const u8 type_color = desc->type_color;

	*color = (type_color >> CQ_DESC_TYPE_BITS) & CQ_DESC_COLOR_MASK;

	/*

	 * Make sure color bit is read from desc *before* other fields

	 * are read from desc.  Hardware guarantees color bit is last

	 * bit (byte) written.  Adding the rmb() prevents the compiler

	 * and/or CPU from reordering the reads which would potentially

	 * result in reading stale values.

	 */

	rmb();

	*type = type_color & CQ_DESC_TYPE_MASK;

	*q_number = le16_to_cpu(desc->q_number) & CQ_DESC_Q_NUM_MASK;

	*completed_index = le16_to_cpu(desc->completed_index) &

		CQ_DESC_COMP_NDX_MASK;

}

#endif /* _CQ_DESC_H_ */