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Commit f46c0120 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: display watermark updates (v2) 



- Add module option to force the display priority
  0 = auto, 1 = normal, 2 = high
- Default to high on r3xx/r4xx/rv515 chips
  Fixes flickering problems during heavy acceleration
  due to underflow to the display controllers
- Fill in minimal support for RS600

v2 - update display priority when bandwidth is updated
so the user can change the parameter at runtime and it
will take affect on the next modeset.

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 3b01a119

drivers/gpu/drm/radeon/r100.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -2389,6 +2389,8 @@ void r100_bandwidth_update(struct radeon_device *rdev) 
	uint32_t pixel_bytes1 = 0;

	uint32_t pixel_bytes1 = 0;

	uint32_t pixel_bytes2 = 0;

	uint32_t pixel_bytes2 = 0;





	radeon_update_display_priority(rdev);



	if (rdev->mode_info.crtcs[0]->base.enabled) {

	if (rdev->mode_info.crtcs[0]->base.enabled) {

		mode1 = &rdev->mode_info.crtcs[0]->base.mode;

		mode1 = &rdev->mode_info.crtcs[0]->base.mode;

		pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;

		pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;

drivers/gpu/drm/radeon/radeon.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -91,6 +91,7 @@ extern int radeon_tv; 
extern int radeon_new_pll;

extern int radeon_new_pll;

extern int radeon_dynpm;

extern int radeon_dynpm;

extern int radeon_audio;

extern int radeon_audio;

extern int radeon_disp_priority;





/*

/*

 * Copy from radeon_drv.h so we don't have to include both and have conflicting

 * Copy from radeon_drv.h so we don't have to include both and have conflicting
@@ -1181,6 +1182,7 @@ extern int radeon_modeset_init(struct radeon_device *rdev); 
extern void radeon_modeset_fini(struct radeon_device *rdev);

extern void radeon_modeset_fini(struct radeon_device *rdev);

extern bool radeon_card_posted(struct radeon_device *rdev);

extern bool radeon_card_posted(struct radeon_device *rdev);

extern void radeon_update_bandwidth_info(struct radeon_device *rdev);

extern void radeon_update_bandwidth_info(struct radeon_device *rdev);

extern void radeon_update_display_priority(struct radeon_device *rdev);

extern bool radeon_boot_test_post_card(struct radeon_device *rdev);

extern bool radeon_boot_test_post_card(struct radeon_device *rdev);

extern int radeon_clocks_init(struct radeon_device *rdev);

extern int radeon_clocks_init(struct radeon_device *rdev);

extern void radeon_clocks_fini(struct radeon_device *rdev);

extern void radeon_clocks_fini(struct radeon_device *rdev);

drivers/gpu/drm/radeon/radeon_display.c

+17 −0
Original line number Original line Diff line number Diff line
@@ -971,6 +971,23 @@ static int radeon_modeset_create_props(struct radeon_device *rdev) 
	return 0;

	return 0;

}

}





void radeon_update_display_priority(struct radeon_device *rdev)

{

	/* adjustment options for the display watermarks */

	if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {

		/* set display priority to high for r3xx, rv515 chips

		 * this avoids flickering due to underflow to the

		 * display controllers during heavy acceleration.

		 */

		if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515))

			rdev->disp_priority = 2;

		else

			rdev->disp_priority = 0;

	} else

		rdev->disp_priority = radeon_disp_priority;



}



int radeon_modeset_init(struct radeon_device *rdev)

int radeon_modeset_init(struct radeon_device *rdev)

{

{

	int i;

	int i;

drivers/gpu/drm/radeon/radeon_drv.c

+4 −0
Original line number Original line Diff line number Diff line
@@ -92,6 +92,7 @@ int radeon_tv = 1; 
int radeon_new_pll = -1;

int radeon_new_pll = -1;

int radeon_dynpm = -1;

int radeon_dynpm = -1;

int radeon_audio = 1;

int radeon_audio = 1;

int radeon_disp_priority = 0;





MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");

MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");

module_param_named(no_wb, radeon_no_wb, int, 0444);

module_param_named(no_wb, radeon_no_wb, int, 0444);
@@ -135,6 +136,9 @@ module_param_named(dynpm, radeon_dynpm, int, 0444); 
MODULE_PARM_DESC(audio, "Audio enable (0 = disable)");

MODULE_PARM_DESC(audio, "Audio enable (0 = disable)");

module_param_named(audio, radeon_audio, int, 0444);

module_param_named(audio, radeon_audio, int, 0444);





MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");

module_param_named(disp_priority, radeon_disp_priority, int, 0444);



static int radeon_suspend(struct drm_device *dev, pm_message_t state)

static int radeon_suspend(struct drm_device *dev, pm_message_t state)

{

{

	drm_radeon_private_t *dev_priv = dev->dev_private;

	drm_radeon_private_t *dev_priv = dev->dev_private;

drivers/gpu/drm/radeon/rs600.c

+24 −1
Original line number Original line Diff line number Diff line
@@ -483,7 +483,30 @@ void rs600_mc_init(struct radeon_device *rdev) 




void rs600_bandwidth_update(struct radeon_device *rdev)

void rs600_bandwidth_update(struct radeon_device *rdev)

{

{

	/* FIXME: implement, should this be like rs690 ? */

	struct drm_display_mode *mode0 = NULL;

	struct drm_display_mode *mode1 = NULL;

	u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;

	/* FIXME: implement full support */



	radeon_update_display_priority(rdev);



	if (rdev->mode_info.crtcs[0]->base.enabled)

		mode0 = &rdev->mode_info.crtcs[0]->base.mode;

	if (rdev->mode_info.crtcs[1]->base.enabled)

		mode1 = &rdev->mode_info.crtcs[1]->base.mode;



	rs690_line_buffer_adjust(rdev, mode0, mode1);



	if (rdev->disp_priority == 2) {

		d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);

		d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);

		d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);

		d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);

		WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);

		WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);

		WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);

		WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);

	}

}

}





uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)

uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)