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Commit 466eed22 authored by Alan Cox's avatar Alan Cox Committed by Ingo Molnar
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x86: isolate PIC/PIT in/out calls 



Rather than remove and/or mangle inb_p/outb_p we want to remove the use
of them from inappropriate places. For the PIC/PIT this may eventually
depend on 32/64bitism or similar so start by adding inb/outb_pit and
inb/outb_pic so that we can make them use any scheme we settle on without
disturbing the existing, correct (for ISA), port 0x80 usage. (eg we can
make inb_pit use udelay without messing up inb_p).

Floppy already does this for the fdc. That really only leaves the CMOS as
a core logic item to tackle, and bits of parallel port handling in the
chipset layers.

Signed-off-by: default avatarAlan Cox <alan@redhat.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent fb8830e7

arch/x86/kernel/apm_32.c

+3 −3
Original line number Diff line number Diff line
@@ -1174,11 +1174,11 @@ static void reinit_timer(void) 


	spin_lock_irqsave(&i8253_lock, flags);

	/* set the clock to HZ */

	outb_p(0x34, PIT_MODE);		/* binary, mode 2, LSB/MSB, ch 0 */

	outb_pit(0x34, PIT_MODE);		/* binary, mode 2, LSB/MSB, ch 0 */

	udelay(10);

	outb_p(LATCH & 0xff, PIT_CH0);	/* LSB */

	outb_pit(LATCH & 0xff, PIT_CH0);	/* LSB */

	udelay(10);

	outb(LATCH >> 8, PIT_CH0);	/* MSB */

	outb_pit(LATCH >> 8, PIT_CH0);	/* MSB */

	udelay(10);

	spin_unlock_irqrestore(&i8253_lock, flags);

#endif

arch/x86/kernel/i8253.c

+15 −15
Original line number Diff line number Diff line
@@ -43,26 +43,26 @@ static void init_pit_timer(enum clock_event_mode mode, 
	switch(mode) {

	case CLOCK_EVT_MODE_PERIODIC:

		/* binary, mode 2, LSB/MSB, ch 0 */

		outb_p(0x34, PIT_MODE);

		outb_p(LATCH & 0xff , PIT_CH0);	/* LSB */

		outb(LATCH >> 8 , PIT_CH0);	/* MSB */

		outb_pit(0x34, PIT_MODE);

		outb_pit(LATCH & 0xff , PIT_CH0);	/* LSB */

		outb_pit(LATCH >> 8 , PIT_CH0);		/* MSB */

		break;



	case CLOCK_EVT_MODE_SHUTDOWN:

	case CLOCK_EVT_MODE_UNUSED:

		if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||

		    evt->mode == CLOCK_EVT_MODE_ONESHOT) {

			outb_p(0x30, PIT_MODE);

			outb_p(0, PIT_CH0);

			outb_p(0, PIT_CH0);

			outb_pit(0x30, PIT_MODE);

			outb_pit(0, PIT_CH0);

			outb_pit(0, PIT_CH0);

		}

		pit_disable_clocksource();

		break;



	case CLOCK_EVT_MODE_ONESHOT:

		/* One shot setup */

		outb_p(0x38, PIT_MODE);

		pit_disable_clocksource();

		outb_pit(0x38, PIT_MODE);

		break;



	case CLOCK_EVT_MODE_RESUME:
@@ -80,8 +80,8 @@ static void init_pit_timer(enum clock_event_mode mode, 
static int pit_next_event(unsigned long delta, struct clock_event_device *evt)

{

	spin_lock(&i8253_lock);

	outb_p(delta & 0xff , PIT_CH0);	/* LSB */

	outb(delta >> 8 , PIT_CH0);	/* MSB */

	outb_pit(delta & 0xff , PIT_CH0);	/* LSB */

	outb_pit(delta >> 8 , PIT_CH0);		/* MSB */

	spin_unlock(&i8253_lock);



	return 0;
@@ -153,15 +153,15 @@ static cycle_t pit_read(void) 
	 * count), it cannot be newer.

	 */

	jifs = jiffies;

	outb_p(0x00, PIT_MODE);	/* latch the count ASAP */

	count = inb_p(PIT_CH0);	/* read the latched count */

	count |= inb_p(PIT_CH0) << 8;

	outb_pit(0x00, PIT_MODE);	/* latch the count ASAP */

	count = inb_pit(PIT_CH0);	/* read the latched count */

	count |= inb_pit(PIT_CH0) << 8;



	/* VIA686a test code... reset the latch if count > max + 1 */

	if (count > LATCH) {

		outb_p(0x34, PIT_MODE);

		outb_p(LATCH & 0xff, PIT_CH0);

		outb(LATCH >> 8, PIT_CH0);

		outb_pit(0x34, PIT_MODE);

		outb_pit(LATCH & 0xff, PIT_CH0);

		outb_pit(LATCH >> 8, PIT_CH0);

		count = LATCH - 1;

	}

arch/x86/kernel/i8259_32.c

+10 −10
Original line number Diff line number Diff line
@@ -289,20 +289,20 @@ void init_8259A(int auto_eoi) 
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */



	/*

	 * outb_p - this has to work on a wide range of PC hardware.

	 * outb_pic - this has to work on a wide range of PC hardware.

	 */

	outb_p(0x11, PIC_MASTER_CMD);	/* ICW1: select 8259A-1 init */

	outb_p(0x20 + 0, PIC_MASTER_IMR);	/* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */

	outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);	/* 8259A-1 (the master) has a slave on IR2 */

	outb_pic(0x11, PIC_MASTER_CMD);	/* ICW1: select 8259A-1 init */

	outb_pic(0x20 + 0, PIC_MASTER_IMR);	/* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */

	outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);	/* 8259A-1 (the master) has a slave on IR2 */

	if (auto_eoi)	/* master does Auto EOI */

		outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);

		outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);

	else		/* master expects normal EOI */

		outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);

		outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);



	outb_p(0x11, PIC_SLAVE_CMD);	/* ICW1: select 8259A-2 init */

	outb_p(0x20 + 8, PIC_SLAVE_IMR);	/* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */

	outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR);	/* 8259A-2 is a slave on master's IR2 */

	outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */

	outb_pic(0x11, PIC_SLAVE_CMD);	/* ICW1: select 8259A-2 init */

	outb_pic(0x20 + 8, PIC_SLAVE_IMR);	/* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */

	outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);	/* 8259A-2 is a slave on master's IR2 */

	outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */

	if (auto_eoi)

		/*

		 * In AEOI mode we just have to mask the interrupt

arch/x86/kernel/i8259_64.c

+10 −10
Original line number Diff line number Diff line
@@ -359,25 +359,25 @@ void init_8259A(int auto_eoi) 
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */



	/*

	 * outb_p - this has to work on a wide range of PC hardware.

	 * outb_pic - this has to work on a wide range of PC hardware.

	 */

	outb_p(0x11, PIC_MASTER_CMD);	/* ICW1: select 8259A-1 init */

	outb_pic(0x11, PIC_MASTER_CMD);	/* ICW1: select 8259A-1 init */

	/* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 */

	outb_p(IRQ0_VECTOR, PIC_MASTER_IMR);

	outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);

	/* 8259A-1 (the master) has a slave on IR2 */

	outb_p(0x04, PIC_MASTER_IMR);

	outb_pic(0x04, PIC_MASTER_IMR);

	if (auto_eoi)	/* master does Auto EOI */

		outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);

		outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);

	else		/* master expects normal EOI */

		outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);

		outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);



	outb_p(0x11, PIC_SLAVE_CMD);	/* ICW1: select 8259A-2 init */

	outb_pic(0x11, PIC_SLAVE_CMD);	/* ICW1: select 8259A-2 init */

	/* ICW2: 8259A-2 IR0-7 mapped to 0x38-0x3f */

	outb_p(IRQ8_VECTOR, PIC_SLAVE_IMR);

	outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);

	/* 8259A-2 is a slave on master's IR2 */

	outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR);

	outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);

	/* (slave's support for AEOI in flat mode is to be investigated) */

	outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);

	outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);



	if (auto_eoi)

		/*

arch/x86/kernel/vmiclock_32.c

+1 −1
Original line number Diff line number Diff line
@@ -237,7 +237,7 @@ static void __devinit vmi_time_init_clockevent(void) 
void __init vmi_time_init(void)

{

	/* Disable PIT: BIOSes start PIT CH0 with 18.2hz peridic. */

	outb_p(0x3a, PIT_MODE); /* binary, mode 5, LSB/MSB, ch 0 */

	outb_pit(0x3a, PIT_MODE); /* binary, mode 5, LSB/MSB, ch 0 */



	vmi_time_init_clockevent();

	setup_irq(0, &vmi_clock_action);