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Commit 0d3e0460 authored by Matthew Fleming's avatar Matthew Fleming Committed by Pierre Ossman
Browse files

MMC: CSD and CID timeout values 



The MMC spec states that the timeout for accessing the CSD and CID
registers is 64 clock cycles.

Signed-off-by: default avatarMatthew Fleming <matthew.fleming@imgtec.com>
Signed-off-by: default avatarPierre Ossman <drzeus@drzeus.cx>
parent 7244b85b

drivers/mmc/core/mmc_ops.c

+6 −2
Original line number Original line Diff line number Diff line
@@ -248,8 +248,12 @@ mmc_send_cxd_data(struct mmc_card *card, struct mmc_host *host, 




	sg_init_one(&sg, data_buf, len);

	sg_init_one(&sg, data_buf, len);





	if (card)

	/*

		mmc_set_data_timeout(&data, card);

	 * The spec states that CSR and CID accesses have a timeout

	 * of 64 clock cycles.

	 */

	data.timeout_ns = 0;

	data.timeout_clks = 64;





	mmc_wait_for_req(host, &mrq);

	mmc_wait_for_req(host, &mrq);