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Commit ffda203c authored by Anish Bhatt's avatar Anish Bhatt Committed by Greg Kroah-Hartman
Browse files

wilc1000 : Use BIT() macro where possible 



Replace (1 << x) by BIT(x) as recommended by
checkpatch.pl

Signed-off-by: default avatarAnish Bhatt <anish@gatech.edu>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 65ead4ec

drivers/staging/wilc1000/host_interface.c

+2 −2
Original line number Diff line number Diff line
@@ -7316,7 +7316,7 @@ static void *host_int_ParseJoinBssParam(tstrNetworkInfo *ptstrNetworkInfo) 
				pNewJoinBssParam->wmm_cap = true;



				/* Check if Bit 7 is set indicating U-APSD capability */

				if (pu8IEs[index + 8] & (1 << 7))

				if (pu8IEs[index + 8] & BIT(7))

					pNewJoinBssParam->uapsd_cap = true;

				index += pu8IEs[index + 1] + 2;

				continue;
@@ -7332,7 +7332,7 @@ static void *host_int_ParseJoinBssParam(tstrNetworkInfo *ptstrNetworkInfo) 
				pNewJoinBssParam->u8Index = pu8IEs[index + 9];



				/* Check if Bit 7 is set indicating Opss capability */

				if (pu8IEs[index + 10] & (1 << 7)) {

				if (pu8IEs[index + 10] & BIT(7)) {

					pNewJoinBssParam->u8OppEnable = 1;

					pNewJoinBssParam->u8CtWindow = pu8IEs[index + 10];

				} else

drivers/staging/wilc1000/host_interface.h

+19 −19
Original line number Diff line number Diff line
@@ -138,25 +138,25 @@ typedef struct { 
} tstrCfgParamVal;



typedef enum {

	RETRY_SHORT		= 1 << 0,

	RETRY_LONG		= 1 << 1,

	FRAG_THRESHOLD		= 1 << 2,

	RTS_THRESHOLD		= 1 << 3,

	BSS_TYPE		= 1 << 4,

	AUTH_TYPE		= 1 << 5,

	AUTHEN_TIMEOUT		= 1 << 6,

	POWER_MANAGEMENT	= 1 << 7,

	PREAMBLE		= 1 << 8,

	SHORT_SLOT_ALLOWED	= 1 << 9,

	TXOP_PROT_DISABLE	= 1 << 10,

	BEACON_INTERVAL		= 1 << 11,

	DTIM_PERIOD		= 1 << 12,

	SITE_SURVEY		= 1 << 13,

	SITE_SURVEY_SCAN_TIME	= 1 << 14,

	ACTIVE_SCANTIME		= 1 << 15,

	PASSIVE_SCANTIME	= 1 << 16,

	CURRENT_TX_RATE		= 1 << 17,

	HT_ENABLE		= 1 << 18,

	RETRY_SHORT		= BIT(0),

	RETRY_LONG		= BIT(1),

	FRAG_THRESHOLD		= BIT(2),

	RTS_THRESHOLD		= BIT(3),

	BSS_TYPE		= BIT(4),

	AUTH_TYPE		= BIT(5),

	AUTHEN_TIMEOUT		= BIT(6),

	POWER_MANAGEMENT	= BIT(7),

	PREAMBLE		= BIT(8),

	SHORT_SLOT_ALLOWED	= BIT(9),

	TXOP_PROT_DISABLE	= BIT(10),

	BEACON_INTERVAL		= BIT(11),

	DTIM_PERIOD		= BIT(12),

	SITE_SURVEY		= BIT(13),

	SITE_SURVEY_SCAN_TIME	= BIT(14),

	ACTIVE_SCANTIME		= BIT(15),

	PASSIVE_SCANTIME	= BIT(16),

	CURRENT_TX_RATE		= BIT(17),

	HT_ENABLE		= BIT(18),

} tenuCfgParam;



typedef struct {

drivers/staging/wilc1000/linux_wlan_common.h

+4 −4
Original line number Diff line number Diff line
@@ -44,10 +44,10 @@ void wilc_debugfs_remove(void); 
extern atomic_t REGION;

extern atomic_t DEBUG_LEVEL;



#define DEBUG           (1 << 0)

#define INFO            (1 << 1)

#define WRN             (1 << 2)

#define ERR             (1 << 3)

#define DEBUG           BIT(0)

#define INFO            BIT(1)

#define WRN             BIT(2)

#define ERR             BIT(3)



#define PRINT_D(region, ...)						\

	do {								\

drivers/staging/wilc1000/wilc_sdio.c

+22 −22
Original line number Diff line number Diff line
@@ -529,7 +529,7 @@ static int sdio_sync(void) 
		return 0;

	}



	reg &= ~(1 << 8);

	reg &= ~BIT(8);

	if (!sdio_write_reg(WILC_MISC, reg)) {

		g_sdio.dPrint(N_ERR, "[wilc sdio]: Failed write misc reg...\n");

		return 0;
@@ -548,7 +548,7 @@ static int sdio_sync(void) 
			g_sdio.dPrint(N_ERR, "[wilc spi]: Failed read reg (%08x)...\n", WILC_PIN_MUX_0);

			return 0;

		}

		reg |= (1 << 8);

		reg |= BIT(8);

		ret = sdio_write_reg(WILC_PIN_MUX_0, reg);

		if (!ret) {

			g_sdio.dPrint(N_ERR, "[wilc spi]: Failed write reg (%08x)...\n", WILC_PIN_MUX_0);
@@ -563,7 +563,7 @@ static int sdio_sync(void) 
			g_sdio.dPrint(N_ERR, "[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR_ENABLE);

			return 0;

		}

		reg |= (1 << 16);

		reg |= BIT(16);

		ret = sdio_write_reg(WILC_INTR_ENABLE, reg);

		if (!ret) {

			g_sdio.dPrint(N_ERR, "[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR_ENABLE);
@@ -756,17 +756,17 @@ static int sdio_read_int(u32 *int_status) 
	cmd.data = 0;

	g_sdio.sdio_cmd52(&cmd);



	if (cmd.data & (1 << 0))

	if (cmd.data & BIT(0))

		tmp |= INT_0;

	if (cmd.data & (1 << 2))

	if (cmd.data & BIT(2))

		tmp |= INT_1;

	if (cmd.data & (1 << 3))

	if (cmd.data & BIT(3))

		tmp |= INT_2;

	if (cmd.data & (1 << 4))

	if (cmd.data & BIT(4))

		tmp |= INT_3;

	if (cmd.data & (1 << 5))

	if (cmd.data & BIT(5))

		tmp |= INT_4;

	if (cmd.data & (1 << 6))

	if (cmd.data & BIT(6))

		tmp |= INT_5;

	{

		int i;
@@ -810,7 +810,7 @@ static int sdio_clear_int_ext(u32 val) 
		{

			u32 flags;



			flags = val & ((1 << MAX_NUN_INT_THRPT_ENH2) - 1);

			flags = val & (BIT(MAX_NUN_INT_THRPT_ENH2) - 1);

			reg = flags;

		}

#else
@@ -818,13 +818,13 @@ static int sdio_clear_int_ext(u32 val) 
#endif

		/* select VMM table 0 */

		if ((val & SEL_VMM_TBL0) == SEL_VMM_TBL0)

			reg |= (1 << 5);

			reg |= BIT(5);

		/* select VMM table 1 */

		if ((val & SEL_VMM_TBL1) == SEL_VMM_TBL1)

			reg |= (1 << 6);

			reg |= BIT(6);

		/* enable VMM */

		if ((val & EN_VMM) == EN_VMM)

			reg |= (1 << 7);

			reg |= BIT(7);

		if (reg) {

			sdio_cmd52_t cmd;
@@ -848,7 +848,7 @@ static int sdio_clear_int_ext(u32 val) 
			/* Cannot clear multiple interrupts. Must clear each interrupt individually */

			u32 flags;



			flags = val & ((1 << MAX_NUM_INT) - 1);

			flags = val & (BIT(MAX_NUM_INT) - 1);

			if (flags) {

				int i;
@@ -861,7 +861,7 @@ static int sdio_clear_int_ext(u32 val) 
						cmd.function = 0;

						cmd.raw = 0;

						cmd.address = 0xf8;

						cmd.data = (1 << i);

						cmd.data = BIT(i);



						ret = g_sdio.sdio_cmd52(&cmd);

						if (!ret) {
@@ -891,13 +891,13 @@ static int sdio_clear_int_ext(u32 val) 
			vmm_ctl = 0;

			/* select VMM table 0 */

			if ((val & SEL_VMM_TBL0) == SEL_VMM_TBL0)

				vmm_ctl |= (1 << 0);

				vmm_ctl |= BIT(0);

			/* select VMM table 1 */

			if ((val & SEL_VMM_TBL1) == SEL_VMM_TBL1)

				vmm_ctl |= (1 << 1);

				vmm_ctl |= BIT(1);

			/* enable VMM */

			if ((val & EN_VMM) == EN_VMM)

				vmm_ctl |= (1 << 2);

				vmm_ctl |= BIT(2);



			if (vmm_ctl) {

				sdio_cmd52_t cmd;
@@ -944,7 +944,7 @@ static int sdio_sync_ext(int nint /* how mant interrupts to enable. */) 
		return 0;

	}



	reg &= ~(1 << 8);

	reg &= ~BIT(8);

	if (!sdio_write_reg(WILC_MISC, reg)) {

		g_sdio.dPrint(N_ERR, "[wilc sdio]: Failed write misc reg...\n");

		return 0;
@@ -963,7 +963,7 @@ static int sdio_sync_ext(int nint /* how mant interrupts to enable. */) 
			g_sdio.dPrint(N_ERR, "[wilc sdio]: Failed read reg (%08x)...\n", WILC_PIN_MUX_0);

			return 0;

		}

		reg |= (1 << 8);

		reg |= BIT(8);

		ret = sdio_write_reg(WILC_PIN_MUX_0, reg);

		if (!ret) {

			g_sdio.dPrint(N_ERR, "[wilc sdio]: Failed write reg (%08x)...\n", WILC_PIN_MUX_0);
@@ -980,7 +980,7 @@ static int sdio_sync_ext(int nint /* how mant interrupts to enable. */) 
		}



		for (i = 0; (i < 5) && (nint > 0); i++, nint--)

			reg |= (1 << (27 + i));

			reg |= BIT((27 + i));

		ret = sdio_write_reg(WILC_INTR_ENABLE, reg);

		if (!ret) {

			g_sdio.dPrint(N_ERR, "[wilc sdio]: Failed write reg (%08x)...\n", WILC_INTR_ENABLE);
@@ -994,7 +994,7 @@ static int sdio_sync_ext(int nint /* how mant interrupts to enable. */) 
			}



			for (i = 0; (i < 3) && (nint > 0); i++, nint--)

				reg |= (1 << i);

				reg |= BIT(i);



			ret = sdio_read_reg(WILC_INTR2_ENABLE, &reg);

			if (!ret) {

drivers/staging/wilc1000/wilc_spi.c

+12 −12
Original line number Diff line number Diff line
@@ -128,7 +128,7 @@ static int spi_cmd(u8 cmd, u32 adr, u32 data, u32 sz, u8 clockless) 
	case CMD_INTERNAL_READ:                 /* internal register read */

		bc[1] = (u8)(adr >> 8);

		if (clockless)

			bc[1] |= (1 << 7);

			bc[1] |= BIT(7);

		bc[2] = (u8)adr;

		bc[3] = 0x00;

		len = 5;
@@ -179,7 +179,7 @@ static int spi_cmd(u8 cmd, u32 adr, u32 data, u32 sz, u8 clockless) 
	case CMD_INTERNAL_WRITE:                /* internal register write */

		bc[1] = (u8)(adr >> 8);

		if (clockless)

			bc[1] |= (1 << 7);

			bc[1] |= BIT(7);

		bc[2] = (u8)(adr);

		bc[3] = (u8)(data >> 24);

		bc[4] = (u8)(data >> 16);
@@ -288,7 +288,7 @@ static int spi_cmd_complete(u8 cmd, u32 adr, u8 *b, u32 sz, u8 clockless) 
	case CMD_INTERNAL_READ:                 /* internal register read */

		wb[1] = (u8)(adr >> 8);

		if (clockless == 1)

			wb[1] |= (1 << 7);

			wb[1] |= BIT(7);

		wb[2] = (u8)adr;

		wb[3] = 0x00;

		len = 5;
@@ -339,7 +339,7 @@ static int spi_cmd_complete(u8 cmd, u32 adr, u8 *b, u32 sz, u8 clockless) 
	case CMD_INTERNAL_WRITE:                /* internal register write */

		wb[1] = (u8)(adr >> 8);

		if (clockless == 1)

			wb[1] |= (1 << 7);

			wb[1] |= BIT(7);

		wb[2] = (u8)(adr);

		wb[3] = b[3];

		wb[4] = b[2];
@@ -1048,7 +1048,7 @@ static int spi_sync(void) 
		PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_PIN_MUX_0);

		return 0;

	}

	reg |= (1 << 8);

	reg |= BIT(8);

	ret = spi_write_reg(WILC_PIN_MUX_0, reg);

	if (!ret) {

		PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_PIN_MUX_0);
@@ -1063,7 +1063,7 @@ static int spi_sync(void) 
		PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR_ENABLE);

		return 0;

	}

	reg |= (1 << 16);

	reg |= BIT(16);

	ret = spi_write_reg(WILC_INTR_ENABLE, reg);

	if (!ret) {

		PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR_ENABLE);
@@ -1254,7 +1254,7 @@ static int spi_clear_int_ext(u32 val) 
	} else {

		u32 flags;



		flags = val & ((1 << MAX_NUM_INT) - 1);

		flags = val & (BIT(MAX_NUM_INT) - 1);

		if (flags) {

			int i;
@@ -1284,10 +1284,10 @@ static int spi_clear_int_ext(u32 val) 
			tbl_ctl = 0;

			/* select VMM table 0 */

			if ((val & SEL_VMM_TBL0) == SEL_VMM_TBL0)

				tbl_ctl |= (1 << 0);

				tbl_ctl |= BIT(0);

			/* select VMM table 1 */

			if ((val & SEL_VMM_TBL1) == SEL_VMM_TBL1)

				tbl_ctl |= (1 << 1);

				tbl_ctl |= BIT(1);



			ret = spi_write_reg(WILC_VMM_TBL_CTL, tbl_ctl);

			if (!ret) {
@@ -1331,7 +1331,7 @@ static int spi_sync_ext(int nint /* how mant interrupts to enable. */) 
		PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_PIN_MUX_0);

		return 0;

	}

	reg |= (1 << 8);

	reg |= BIT(8);

	ret = spi_write_reg(WILC_PIN_MUX_0, reg);

	if (!ret) {

		PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_PIN_MUX_0);
@@ -1348,7 +1348,7 @@ static int spi_sync_ext(int nint /* how mant interrupts to enable. */) 
	}



	for (i = 0; (i < 5) && (nint > 0); i++, nint--) {

		reg |= (1 << (27 + i));

		reg |= (BIT((27 + i)));

	}

	ret = spi_write_reg(WILC_INTR_ENABLE, reg);

	if (!ret) {
@@ -1363,7 +1363,7 @@ static int spi_sync_ext(int nint /* how mant interrupts to enable. */) 
		}



		for (i = 0; (i < 3) && (nint > 0); i++, nint--) {

			reg |= (1 << i);

			reg |= BIT(i);

		}



		ret = spi_read_reg(WILC_INTR2_ENABLE, &reg);