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Commit ff846f52 authored by Alexander Duyck's avatar Alexander Duyck Committed by David S. Miller
Browse files

igb: add support for reporting 5GT/s during probe on PCIe Gen2 



This change corrects the fact that we were not reporting Gen2 link speeds
when we were in fact connected at Gen2 rates.

Signed-off-by: default avatarAlexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ef021194

drivers/net/igb/e1000_defines.h

+0 −4
Original line number Original line Diff line number Diff line
@@ -610,11 +610,7 @@ 
#define IGP_LED3_MODE           0x07000000

#define IGP_LED3_MODE           0x07000000





/* PCI/PCI-X/PCI-EX Config space */

/* PCI/PCI-X/PCI-EX Config space */

#define PCIE_LINK_STATUS             0x12

#define PCIE_DEVICE_CONTROL2         0x28

#define PCIE_DEVICE_CONTROL2         0x28



#define PCIE_LINK_WIDTH_MASK         0x3F0

#define PCIE_LINK_WIDTH_SHIFT        4

#define PCIE_DEVICE_CONTROL2_16ms    0x0005

#define PCIE_DEVICE_CONTROL2_16ms    0x0005





#define PHY_REVISION_MASK      0xFFFFFFF0

#define PHY_REVISION_MASK      0xFFFFFFF0

drivers/net/igb/e1000_mac.c

+20 −7
Original line number Original line Diff line number Diff line
@@ -53,17 +53,30 @@ s32 igb_get_bus_info_pcie(struct e1000_hw *hw) 
	u16 pcie_link_status;

	u16 pcie_link_status;





	bus->type = e1000_bus_type_pci_express;

	bus->type = e1000_bus_type_pci_express;

	bus->speed = e1000_bus_speed_2500;





	ret_val = igb_read_pcie_cap_reg(hw,

	ret_val = igb_read_pcie_cap_reg(hw,

					  PCIE_LINK_STATUS,

					PCI_EXP_LNKSTA,

					&pcie_link_status);

					&pcie_link_status);

	if (ret_val)

	if (ret_val) {

		bus->width = e1000_bus_width_unknown;

		bus->width = e1000_bus_width_unknown;

	else

		bus->speed = e1000_bus_speed_unknown;

	} else {

		switch (pcie_link_status & PCI_EXP_LNKSTA_CLS) {

		case PCI_EXP_LNKSTA_CLS_2_5GB:

			bus->speed = e1000_bus_speed_2500;

			break;

		case PCI_EXP_LNKSTA_CLS_5_0GB:

			bus->speed = e1000_bus_speed_5000;

			break;

		default:

			bus->speed = e1000_bus_speed_unknown;

			break;

		}



		bus->width = (enum e1000_bus_width)((pcie_link_status &

		bus->width = (enum e1000_bus_width)((pcie_link_status &

						     PCIE_LINK_WIDTH_MASK) >>

						     PCI_EXP_LNKSTA_NLW) >>

						     PCIE_LINK_WIDTH_SHIFT);

						     PCI_EXP_LNKSTA_NLW_SHIFT);

	}





	reg = rd32(E1000_STATUS);

	reg = rd32(E1000_STATUS);

	bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;

	bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;

drivers/net/igb/igb_main.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -1638,6 +1638,7 @@ static int __devinit igb_probe(struct pci_dev *pdev, 
	dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",

	dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",

		 netdev->name,

		 netdev->name,

		 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :

		 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :

		  (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :

		                                            "unknown"),

		                                            "unknown"),

		 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :

		 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :

		  (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :

		  (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :

include/linux/pci_regs.h

+3 −0
Original line number Original line Diff line number Diff line
@@ -442,7 +442,10 @@ 
#define  PCI_EXP_LNKCTL_LABIE	0x0800	/* Lnk Autonomous Bandwidth Interrupt Enable */

#define  PCI_EXP_LNKCTL_LABIE	0x0800	/* Lnk Autonomous Bandwidth Interrupt Enable */

#define PCI_EXP_LNKSTA		18	/* Link Status */

#define PCI_EXP_LNKSTA		18	/* Link Status */

#define  PCI_EXP_LNKSTA_CLS	0x000f	/* Current Link Speed */

#define  PCI_EXP_LNKSTA_CLS	0x000f	/* Current Link Speed */

#define  PCI_EXP_LNKSTA_CLS_2_5GB 0x01	/* Current Link Speed 2.5GT/s */

#define  PCI_EXP_LNKSTA_CLS_5_0GB 0x02	/* Current Link Speed 5.0GT/s */

#define  PCI_EXP_LNKSTA_NLW	0x03f0	/* Nogotiated Link Width */

#define  PCI_EXP_LNKSTA_NLW	0x03f0	/* Nogotiated Link Width */

#define  PCI_EXP_LNKSTA_NLW_SHIFT 4	/* start of NLW mask in link status */

#define  PCI_EXP_LNKSTA_LT	0x0800	/* Link Training */

#define  PCI_EXP_LNKSTA_LT	0x0800	/* Link Training */

#define  PCI_EXP_LNKSTA_SLC	0x1000	/* Slot Clock Configuration */

#define  PCI_EXP_LNKSTA_SLC	0x1000	/* Slot Clock Configuration */

#define  PCI_EXP_LNKSTA_DLLLA	0x2000	/* Data Link Layer Link Active */

#define  PCI_EXP_LNKSTA_DLLLA	0x2000	/* Data Link Layer Link Active */