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Commit ff7669a1 authored by Mohammed Mirza Mandayappurath Manzoor's avatar Mohammed Mirza Mandayappurath Manzoor
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msm: kgsl: Program QDSS registers to access via coresight interface 



On a6xx, we need to provide access to ISDB registers in QDSS register space
for making an OpenCL profiling tool based on ISDB. This change maps the
registers and provides support for accessing the registers through adb.

Change-Id: I4da8c186d8216e4f00d2f87d9c1089772f00e584
Signed-off-by: default avatarMohammed Mirza Mandayappurath Manzoor <mmandaya@codeaurora.org>
parent 313a025f

Documentation/devicetree/bindings/gpu/adreno.txt

+5 −2
Original line number Diff line number Diff line
@@ -8,7 +8,8 @@ Required properties: 
- reg:			Specifies the register base address and size, the shader memory

			base address and size (if it exists), base address and size

			of the CX_DBGC block (if it exists), and the base address and

			size of the CX_MISC block (if it exists).

			size of the CX_MISC block (if it exists), and the base address and size of

			QDSS_GFX block (if it exists).

- reg-names:		Resource names used for the physical address of device registers

			and shader memory. "kgsl_3d0_reg_memory" gives the physical address

			and length of device registers while "kgsl_3d0_shader_memory" gives
@@ -17,7 +18,9 @@ Required properties: 
			registers used for various configuration options. If specified,

			"kgsl_3d0_cx_dbgc_memory" gives the physical address and length

			of the CX DBGC block. If specified, "cx_misc" gives

			the physical address and length of the CX_MISC block.

			the physical address and length of the CX_MISC block. If specified,

			"qdss_gfx" provides the physical address and length of the

			QDSS_GFX_DBG block.

- interrupts:		Interrupt mapping for GPU IRQ.

- interrupt-names:	String property to describe the name of the interrupt.

- qcom,id:		An integer used as an identification number for the device.

drivers/gpu/msm/a6xx_reg.h

+24 −0
Original line number Diff line number Diff line
@@ -532,6 +532,30 @@ 
#define A6XX_RBBM_CLOCK_DELAY_HLSQ       0x0011c

#define A6XX_RBBM_CLOCK_HYST_HLSQ        0x0011d



/* ISDB SP0 and SP1 registers */

#define A6XX_SP0_ISDB_ISDB_EN                           0xf40001

#define A6XX_SP0_ISDB_ISDB_BRKPT_CFG                    0xf40005

#define A6XX_SP0_ISDB_ISDB_SHADER_ID_CFG                0xf40006

#define A6XX_SP0_ISDB_ISDB_WAVE_ID_CFG                  0xf40007

#define A6XX_SP0_ISDB_ISDB_SAC_CFG                      0xf40024

#define A6XX_SP0_ISDB_ISDB_SAC_ADDR_0                   0xf40020

#define A6XX_SP0_ISDB_ISDB_SAC_ADDR_1                   0xf40021

#define A6XX_SP0_ISDB_ISDB_SAC_MASK_0                   0xf40022

#define A6XX_SP0_ISDB_ISDB_SAC_MASK_1                   0xf40023

#define A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_CTRL      0xf44000

#define A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_X         0xf44001

#define A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_Y         0xf44002

#define A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_Z         0xf44003

#define A6XX_SP1_ISDB_ISDB_EN                           0xf40401

#define A6XX_SP1_ISDB_ISDB_SAC_CFG                      0xf40424

#define A6XX_SP1_ISDB_ISDB_SAC_ADDR_0                   0xf40420

#define A6XX_SP1_ISDB_ISDB_SAC_ADDR_1                   0xf40421

#define A6XX_SP1_ISDB_ISDB_SAC_MASK_0                   0xf40422

#define A6XX_SP1_ISDB_ISDB_SAC_MASK_1                   0xf40423

#define A6XX_SP1_ISDB_ISDB_SHADER_ID_CFG                0xf40406

#define A6XX_SP1_ISDB_ISDB_WAVE_ID_CFG                  0xf40407

#define A6XX_SP1_ISDB_ISDB_BRKPT_CFG                    0xf40405



/* DBGC_CFG registers */

#define A6XX_DBGC_CFG_DBGBUS_SEL_A                  0x600

#define A6XX_DBGC_CFG_DBGBUS_SEL_B                  0x601

drivers/gpu/msm/adreno.c

+23 −0
Original line number Diff line number Diff line
@@ -1240,6 +1240,26 @@ static void adreno_cx_misc_probe(struct kgsl_device *device) 
					res->start, adreno_dev->cx_misc_len);

}



static void adreno_qdss_dbg_probe(struct kgsl_device *device)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct resource *res;



	res = platform_get_resource_byname(device->pdev, IORESOURCE_MEM,

					   "qdss_gfx");



	if (res == NULL)

		return;



	adreno_dev->qdss_gfx_base = res->start - device->reg_phys;

	adreno_dev->qdss_gfx_len = resource_size(res);

	adreno_dev->qdss_gfx_virt = devm_ioremap(device->dev, res->start,

						resource_size(res));



	if (adreno_dev->qdss_gfx_virt == NULL)

		KGSL_DRV_WARN(device, "qdss_gfx ioremap failed\n");

}



static void adreno_efuse_read_soc_hw_rev(struct adreno_device *adreno_dev)

{

	unsigned int val;
@@ -1375,6 +1395,9 @@ static int adreno_probe(struct platform_device *pdev) 
	/* Probe for the optional CX_MISC block */

	adreno_cx_misc_probe(device);



	/*Probe for the optional QDSS_GFX_DBG block*/

	adreno_qdss_dbg_probe(device);



	/*

	 * qcom,iommu-secure-id is used to identify MMUs that can handle secure

	 * content but that is only part of the story - the GPU also has to be

drivers/gpu/msm/adreno.h

+6 −0
Original line number Diff line number Diff line
@@ -443,6 +443,9 @@ enum gpu_coresight_sources { 
 * @chipid: Chip ID specific to the GPU

 * @gmem_base: Base physical address of GMEM

 * @gmem_size: GMEM size

 * @qdss_gfx_base: Base physical address of QDSS_GFX_DBG registers for Coresight

 * @qdss_gfx_len: QDSS_GFX_DBG register size

 * @qdss_gfx_virt: Pointer to virtual address of QDSS_GFX_DBG regiter

 * @cx_misc_len: Length of the CX MISC register block

 * @cx_misc_virt: Pointer where the CX MISC block is mapped

 * @gpucore: Pointer to the adreno_gpu_core structure
@@ -522,6 +525,9 @@ struct adreno_device { 
	unsigned int chipid;

	unsigned long gmem_base;

	unsigned long gmem_size;

	unsigned long qdss_gfx_base;

	unsigned long qdss_gfx_len;

	void __iomem *qdss_gfx_virt;

	unsigned long cx_dbgc_base;

	unsigned int cx_dbgc_len;

	void __iomem *cx_dbgc_virt;

drivers/gpu/msm/adreno_a6xx.c

+155 −2
Original line number Diff line number Diff line
@@ -1784,6 +1784,75 @@ static struct adreno_irq a6xx_irq = { 
	.mask = A6XX_INT_MASK,

};



static bool adreno_is_qdss_dbg_register(struct kgsl_device *device,

		unsigned int offsetwords)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);



	return adreno_dev->qdss_gfx_virt &&

		(offsetwords >= (adreno_dev->qdss_gfx_base >> 2)) &&

		(offsetwords < (adreno_dev->qdss_gfx_base +

				adreno_dev->qdss_gfx_len) >> 2);

}





static void adreno_qdss_gfx_dbg_regread(struct kgsl_device *device,

	unsigned int offsetwords, unsigned int *value)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	unsigned int qdss_gfx_offset;



	if (!adreno_is_qdss_dbg_register(device, offsetwords))

		return;



	qdss_gfx_offset = (offsetwords << 2) - adreno_dev->qdss_gfx_base;

	*value = __raw_readl(adreno_dev->qdss_gfx_virt + qdss_gfx_offset);



	/*

	 * ensure this read finishes before the next one.

	 * i.e. act like normal readl()

	 */

	rmb();

}



static void adreno_qdss_gfx_dbg_regwrite(struct kgsl_device *device,

	unsigned int offsetwords, unsigned int value)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	unsigned int qdss_gfx_offset;



	if (!adreno_is_qdss_dbg_register(device, offsetwords))

		return;



	qdss_gfx_offset = (offsetwords << 2) - adreno_dev->qdss_gfx_base;

	trace_kgsl_regwrite(device, offsetwords, value);



	/*

	 * ensure previous writes post before this one,

	 * i.e. act like normal writel()

	 */

	wmb();

	__raw_writel(value, adreno_dev->qdss_gfx_virt + qdss_gfx_offset);

}



static void adreno_gx_regread(struct kgsl_device *device,

	unsigned int offsetwords, unsigned int *value)

{

	if (adreno_is_qdss_dbg_register(device, offsetwords))

		adreno_qdss_gfx_dbg_regread(device, offsetwords, value);

	else

		kgsl_regread(device, offsetwords, value);

}



static void adreno_gx_regwrite(struct kgsl_device *device,

	unsigned int offsetwords, unsigned int value)

{

	if (adreno_is_qdss_dbg_register(device, offsetwords))

		adreno_qdss_gfx_dbg_regwrite(device, offsetwords, value);

	else

		kgsl_regwrite(device, offsetwords, value);

}



static struct adreno_coresight_register a6xx_coresight_regs[] = {

	{ A6XX_DBGC_CFG_DBGBUS_SEL_A },

	{ A6XX_DBGC_CFG_DBGBUS_SEL_B },
@@ -1837,6 +1906,28 @@ static struct adreno_coresight_register a6xx_coresight_regs[] = { 
	{ A6XX_DBGC_PERF_ATB_DRAIN_CMD },

	{ A6XX_DBGC_ECO_CNTL },

	{ A6XX_DBGC_AHB_DBG_CNTL },

	{ A6XX_SP0_ISDB_ISDB_EN },

	{ A6XX_SP0_ISDB_ISDB_SAC_CFG },

	{ A6XX_SP0_ISDB_ISDB_SAC_ADDR_0 },

	{ A6XX_SP0_ISDB_ISDB_SAC_ADDR_1 },

	{ A6XX_SP0_ISDB_ISDB_SAC_MASK_0 },

	{ A6XX_SP0_ISDB_ISDB_SAC_MASK_1 },

	{ A6XX_SP0_ISDB_ISDB_SHADER_ID_CFG },

	{ A6XX_SP0_ISDB_ISDB_WAVE_ID_CFG },

	{ A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_CTRL },

	{ A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_X },

	{ A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_Y },

	{ A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_Z },

	{ A6XX_SP0_ISDB_ISDB_BRKPT_CFG },

	{ A6XX_SP1_ISDB_ISDB_EN },

	{ A6XX_SP1_ISDB_ISDB_SAC_CFG },

	{ A6XX_SP1_ISDB_ISDB_SAC_ADDR_0 },

	{ A6XX_SP1_ISDB_ISDB_SAC_ADDR_1 },

	{ A6XX_SP1_ISDB_ISDB_SAC_MASK_0 },

	{ A6XX_SP1_ISDB_ISDB_SAC_MASK_1 },

	{ A6XX_SP1_ISDB_ISDB_SHADER_ID_CFG },

	{ A6XX_SP1_ISDB_ISDB_WAVE_ID_CFG },

	{ A6XX_SP1_ISDB_ISDB_BRKPT_CFG },

};



static struct adreno_coresight_register a6xx_coresight_regs_cx[] = {
@@ -1948,6 +2039,46 @@ static ADRENO_CORESIGHT_ATTR(perf_atb_trig_intf_sel_1, 
static ADRENO_CORESIGHT_ATTR(perf_atb_drain_cmd, &a6xx_coresight_regs[49]);

static ADRENO_CORESIGHT_ATTR(eco_cntl, &a6xx_coresight_regs[50]);

static ADRENO_CORESIGHT_ATTR(ahb_dbg_cntl, &a6xx_coresight_regs[51]);

static ADRENO_CORESIGHT_ATTR(sp0_isdb_isdb_en, &a6xx_coresight_regs[52]);

static ADRENO_CORESIGHT_ATTR(sp0_isdb_isdb_sac_cfg, &a6xx_coresight_regs[53]);

static ADRENO_CORESIGHT_ATTR(sp0_isdb_isdb_sac_addr_0,

				&a6xx_coresight_regs[54]);

static ADRENO_CORESIGHT_ATTR(sp0_isdb_isdb_sac_addr_1,

				&a6xx_coresight_regs[55]);

static ADRENO_CORESIGHT_ATTR(sp0_isdb_isdb_sac_mask_0,

				&a6xx_coresight_regs[56]);

static ADRENO_CORESIGHT_ATTR(sp0_isdb_isdb_sac_mask_1,

				&a6xx_coresight_regs[57]);

static ADRENO_CORESIGHT_ATTR(sp0_isdb_isdb_shader_id_cfg,

				&a6xx_coresight_regs[58]);

static ADRENO_CORESIGHT_ATTR(sp0_isdb_isdb_wave_id_cfg,

				&a6xx_coresight_regs[59]);

static ADRENO_CORESIGHT_ATTR(hlsq_isdb_isdb_hlsq_isdb_cl_wgid_ctrl,

				&a6xx_coresight_regs[60]);

static ADRENO_CORESIGHT_ATTR(hlsq_isdb_isdb_hlsq_isdb_cl_wgid_x,

				&a6xx_coresight_regs[61]);

static ADRENO_CORESIGHT_ATTR(hlsq_isdb_isdb_hlsq_isdb_cl_wgid_y,

				&a6xx_coresight_regs[62]);

static ADRENO_CORESIGHT_ATTR(hlsq_isdb_isdb_hlsq_isdb_cl_wgid_z,

				&a6xx_coresight_regs[63]);

static ADRENO_CORESIGHT_ATTR(sp0_isdb_isdb_brkpt_cfg, &a6xx_coresight_regs[64]);

static ADRENO_CORESIGHT_ATTR(sp1_isdb_isdb_en, &a6xx_coresight_regs[65]);

static ADRENO_CORESIGHT_ATTR(sp1_isdb_isdb_sac_cfg, &a6xx_coresight_regs[66]);

static ADRENO_CORESIGHT_ATTR(sp1_isdb_isdb_sac_addr_0,

				&a6xx_coresight_regs[67]);

static ADRENO_CORESIGHT_ATTR(sp1_isdb_isdb_sac_addr_1,

				&a6xx_coresight_regs[68]);

static ADRENO_CORESIGHT_ATTR(sp1_isdb_isdb_sac_mask_0,

				&a6xx_coresight_regs[69]);

static ADRENO_CORESIGHT_ATTR(sp1_isdb_isdb_sac_mask_1,

				&a6xx_coresight_regs[70]);

static ADRENO_CORESIGHT_ATTR(sp1_isdb_isdb_shader_id_cfg,

				&a6xx_coresight_regs[71]);

static ADRENO_CORESIGHT_ATTR(sp1_isdb_isdb_wave_id_cfg,

				&a6xx_coresight_regs[72]);

static ADRENO_CORESIGHT_ATTR(sp1_isdb_isdb_brkpt_cfg,

				&a6xx_coresight_regs[73]);





/*CX debug registers*/

static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_sel_a,
@@ -2108,6 +2239,28 @@ static struct attribute *a6xx_coresight_attrs[] = { 
	&coresight_attr_perf_atb_drain_cmd.attr.attr,

	&coresight_attr_eco_cntl.attr.attr,

	&coresight_attr_ahb_dbg_cntl.attr.attr,

	&coresight_attr_sp0_isdb_isdb_en.attr.attr,

	&coresight_attr_sp0_isdb_isdb_sac_cfg.attr.attr,

	&coresight_attr_sp0_isdb_isdb_sac_addr_0.attr.attr,

	&coresight_attr_sp0_isdb_isdb_sac_addr_1.attr.attr,

	&coresight_attr_sp0_isdb_isdb_sac_mask_0.attr.attr,

	&coresight_attr_sp0_isdb_isdb_sac_mask_1.attr.attr,

	&coresight_attr_sp0_isdb_isdb_shader_id_cfg.attr.attr,

	&coresight_attr_sp0_isdb_isdb_wave_id_cfg.attr.attr,

	&coresight_attr_hlsq_isdb_isdb_hlsq_isdb_cl_wgid_ctrl.attr.attr,

	&coresight_attr_hlsq_isdb_isdb_hlsq_isdb_cl_wgid_x.attr.attr,

	&coresight_attr_hlsq_isdb_isdb_hlsq_isdb_cl_wgid_y.attr.attr,

	&coresight_attr_hlsq_isdb_isdb_hlsq_isdb_cl_wgid_z.attr.attr,

	&coresight_attr_sp0_isdb_isdb_brkpt_cfg.attr.attr,

	&coresight_attr_sp1_isdb_isdb_en.attr.attr,

	&coresight_attr_sp1_isdb_isdb_sac_cfg.attr.attr,

	&coresight_attr_sp1_isdb_isdb_sac_addr_0.attr.attr,

	&coresight_attr_sp1_isdb_isdb_sac_addr_1.attr.attr,

	&coresight_attr_sp1_isdb_isdb_sac_mask_0.attr.attr,

	&coresight_attr_sp1_isdb_isdb_sac_mask_1.attr.attr,

	&coresight_attr_sp1_isdb_isdb_shader_id_cfg.attr.attr,

	&coresight_attr_sp1_isdb_isdb_wave_id_cfg.attr.attr,

	&coresight_attr_sp1_isdb_isdb_brkpt_cfg.attr.attr,

	NULL,

};
@@ -2190,8 +2343,8 @@ static struct adreno_coresight a6xx_coresight = { 
	.registers = a6xx_coresight_regs,

	.count = ARRAY_SIZE(a6xx_coresight_regs),

	.groups = a6xx_coresight_groups,

	.read = kgsl_regread,

	.write = kgsl_regwrite,

	.read = adreno_gx_regread,

	.write = adreno_gx_regwrite,

};



static struct adreno_coresight a6xx_coresight_cx = {