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Commit ff5b311d authored by Divya Sharma's avatar Divya Sharma
Browse files

Revert "perf: Add workaround for performance monitor irq burst" 



This reverts commit 9f766b5d.

Change-Id: I255e4ed3972b168d0ab191183268ad98990a6f9b
Signed-off-by: default avatarDivya Sharma <divyash@codeaurora.org>
parent e7c78283

arch/arm64/kernel/perf_event.c

+2 −46
Original line number Diff line number Diff line
@@ -678,31 +678,6 @@ static void armv8pmu_disable_event(struct perf_event *event) 
	raw_spin_unlock_irqrestore(&events->pmu_lock, flags);

}



static inline u32 armv8pmu_get_enabled_ints(void)

{

	u32 int_enset;

	int_enset = read_sysreg(pmintenset_el1);

	write_sysreg(0xffffffff, pmintenclr_el1);

	isb();

	return int_enset;

}



static inline u32 armv8pmu_update_enabled_ints(u32 value, int idx, int set)

{

	if(set)

		value |=  BIT(ARMV8_IDX_TO_COUNTER(idx));

	else

		value &= ~(BIT(ARMV8_IDX_TO_COUNTER(idx)));



	return value;

}



static inline void armv8pmu_set_enabled_ints(u32 mask)

{

	write_sysreg(mask, pmintenset_el1);

	isb();

}



static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev)

{

	u32 pmovsr;
@@ -711,12 +686,6 @@ static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev) 
	struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);

	struct pt_regs *regs;

	int idx;

	u32 enabled_ints;



	/*

	 * Get enabled the PMU interrupts and mask all PMU interrupts.

	 */

	enabled_ints = armv8pmu_get_enabled_ints();



	/*

	 * Get and reset the IRQ flags
@@ -726,10 +695,8 @@ static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev) 
	/*

	 * Did an overflow occur?

	 */

	if (!armv8pmu_has_overflowed(pmovsr)) {

		BUG_ON(1);

	if (!armv8pmu_has_overflowed(pmovsr))

		return IRQ_NONE;

	}



	/*

	 * Handle the counter(s) overflow(s)
@@ -757,14 +724,8 @@ static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev) 
		if (!armpmu_event_set_period(event))

			continue;



		if (perf_event_overflow(event, &data, regs)) {

		if (perf_event_overflow(event, &data, regs))

			cpu_pmu->disable(event);



			/*

			 * Update the list of interrupts that should be reenabled.

			 */

			enabled_ints = armv8pmu_update_enabled_ints(enabled_ints, idx, 0);

		}

	}



	/*
@@ -776,11 +737,6 @@ static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev) 
	 */

	irq_work_run();



	/*

	 * Re-enable the PMU interrupts

	 */

	armv8pmu_set_enabled_ints(enabled_ints);



	return IRQ_HANDLED;

}