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Commit ff37729f authored by Veera Sundaram Sankaran's avatar Veera Sundaram Sankaran
Browse files

drm: msm: update rsc single TCS execution time wait 



Update the single TCS execution time wait for rsc
version-2 based on the hardware programming recommendation.

Change-Id: Iecab6f37971e9c85633e6d2fe5da06b1d175d2e2
Signed-off-by: default avatarVeera Sundaram Sankaran <veeras@codeaurora.org>
parent 4126e402

drivers/gpu/drm/msm/sde_rsc.c

+21 −16
Original line number Diff line number Diff line
@@ -33,20 +33,11 @@ 
#define SDE_RSC_DRV_DBG_NAME		"sde_rsc_drv"

#define SDE_RSC_WRAPPER_DBG_NAME	"sde_rsc_wrapper"



/* worst case time to execute the one tcs vote(sleep/wake) - ~1ms */

#define SINGLE_TCS_EXECUTION_TIME				1064000

#define SINGLE_TCS_EXECUTION_TIME_V1	1064000

#define SINGLE_TCS_EXECUTION_TIME_V2	850000



/* this time is ~1ms - only wake tcs in any mode */

#define RSC_BACKOFF_TIME_NS		 (SINGLE_TCS_EXECUTION_TIME + 100)



/**

 * this time is ~1ms - only wake TCS in mode-0.

 * This time must be greater than backoff time.

 */

#define RSC_MODE_THRESHOLD_TIME_IN_NS	(RSC_BACKOFF_TIME_NS + 2700)



/* this time is ~2ms - sleep+ wake TCS in mode-1 */

#define RSC_TIME_SLOT_0_NS		((SINGLE_TCS_EXECUTION_TIME * 2) + 100)

#define RSC_MODE_INSTRUCTION_TIME	100

#define RSC_MODE_THRESHOLD_OVERHEAD	2700



#define DEFAULT_PANEL_FPS		60

#define DEFAULT_PANEL_JITTER_NUMERATOR	2
@@ -338,9 +329,9 @@ static u32 sde_rsc_timer_calculate(struct sde_rsc_priv *rsc, 
	struct sde_rsc_cmd_config *cmd_config)

{

	const u32 cxo_period_ns = 52;

	u64 rsc_backoff_time_ns = RSC_BACKOFF_TIME_NS;

	u64 rsc_mode_threshold_time_ns = RSC_MODE_THRESHOLD_TIME_IN_NS;

	u64 rsc_time_slot_0_ns = RSC_TIME_SLOT_0_NS;

	u64 rsc_backoff_time_ns = rsc->backoff_time_ns;

	u64 rsc_mode_threshold_time_ns = rsc->mode_threshold_time_ns;

	u64 rsc_time_slot_0_ns = rsc->time_slot_0_ns;

	u64 rsc_time_slot_1_ns;

	const u64 pdc_jitter = 20; /* 20% more */
@@ -1354,6 +1345,20 @@ static int sde_rsc_probe(struct platform_device *pdev) 
	of_property_read_u32(pdev->dev.of_node, "qcom,sde-rsc-version",

								&rsc->version);



	if (rsc->version == SDE_RSC_REV_2)

		rsc->single_tcs_execution_time = SINGLE_TCS_EXECUTION_TIME_V2;

	else

		rsc->single_tcs_execution_time = SINGLE_TCS_EXECUTION_TIME_V1;



	rsc->backoff_time_ns = rsc->single_tcs_execution_time

					+ RSC_MODE_INSTRUCTION_TIME;



	rsc->mode_threshold_time_ns = rsc->backoff_time_ns

					+ RSC_MODE_THRESHOLD_OVERHEAD;



	rsc->time_slot_0_ns = (rsc->single_tcs_execution_time * 2)

					+ RSC_MODE_INSTRUCTION_TIME;



	ret = sde_power_resource_init(pdev, &rsc->phandle);

	if (ret) {

		pr_err("sde rsc:power resource init failed ret:%d\n", ret);

drivers/gpu/drm/msm/sde_rsc_hw.c

+0 −3
Original line number Diff line number Diff line
@@ -103,9 +103,6 @@ 
#define SDE_RSC_MODE_1_VAL		1

#define MAX_MODE2_ENTRY_TRY		3



#define SDE_RSC_REV_1			0x1

#define SDE_RSC_REV_2			0x2



static void rsc_event_trigger(struct sde_rsc_priv *rsc, uint32_t event_type)

{

	struct sde_rsc_event *event;

drivers/gpu/drm/msm/sde_rsc_priv.h

+14 −0
Original line number Diff line number Diff line
@@ -32,6 +32,9 @@ 


#define MAX_COUNT_SIZE_SUPPORTED	128



#define SDE_RSC_REV_1			0x1

#define SDE_RSC_REV_2			0x2



struct sde_rsc_priv;



/**
@@ -148,6 +151,12 @@ struct sde_rsc_timer_config { 
 *			invalid state. It can be blocked by this boolean entry.

 * primary_client:	A client which is allowed to make command state request

 *			and ab/ib vote on display rsc

 * single_tcs_execution_time: worst case time to execute one tcs vote

 *			(sleep/wake)

 * backoff_time_ns:	time to only wake tcs in any mode

 * mode_threshold_time_ns: time to wake TCS in mode-0, must be greater than

 *			backoff time

 * time_slot_0_ns:	time for sleep & wake TCS in mode-1

 * master_drm:		Primary client waits for vsync on this drm object based

 *			on crtc id

 * rsc_vsync_wait:   Refcount to indicate if we have to wait for the vsync.
@@ -180,6 +189,11 @@ struct sde_rsc_priv { 
	bool power_collapse_block;

	struct sde_rsc_client *primary_client;



	u32 single_tcs_execution_time;

	u32 backoff_time_ns;

	u32 mode_threshold_time_ns;

	u32 time_slot_0_ns;



	struct drm_device *master_drm;

	atomic_t rsc_vsync_wait;

	wait_queue_head_t rsc_vsync_waitq;