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Commit fea966f7 authored by Stuart Menefy's avatar Stuart Menefy Committed by Paul Mundt
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sh: Remove implicit sign extension from assembler immediates



The SH instruction set has several instructions which accept an 8 bit
immediate operand. For logical instructions this operand is zero extended,
for arithmetic instructions the operand is sign extended. After adding an
option to the assembler to check this, it was found that several pieces
of assembly code were assuming this behaviour, and in one case
getting it wrong.

So this patch explicitly sign extends any immediate operands, which makes
it obvious what is happening, and fixes the one case which got it wrong.

Signed-off-by: default avatarStuart Menefy <stuart.menefy@st.com>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent d724a9c9
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+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ startup:
	bt	clear_bss
	sub	r0, r2
	mov.l	bss_start_addr, r0
	mov	#0xe0, r1
	mov	#0xffffffe0, r1
	and	r1, r0			! align cache line
	mov.l	text_start_addr, r3
	mov	r0, r1
+1 −1
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@
	.endm

	.macro	sti
	mov	#0xf0, r11
	mov	#0xfffffff0, r11
	extu.b	r11, r11
	not	r11, r11
	stc	sr, r10
+1 −1
Original line number Diff line number Diff line
@@ -257,7 +257,7 @@ restore_all:
	!
	! Calculate new SR value
	mov	k3, k2			! original SR value
	mov	#0xf0, k1
	mov	#0xfffffff0, k1
	extu.b	k1, k1
	not	k1, k1
	and	k1, k2			! Mask original SR value
+3 −2
Original line number Diff line number Diff line
@@ -98,8 +98,9 @@ need_resched:

	mov	#OFF_SR, r0
	mov.l	@(r0,r15), r0		! get status register
	and	#0xf0, r0		! interrupts off (exception path)?
	cmp/eq	#0xf0, r0
	shlr	r0
	and	#(0xf0>>1), r0		! interrupts off (exception path)?
	cmp/eq	#(0xf0>>1), r0
	bt	noresched
	mov.l	3f, r0
	jsr	@r0			! call preempt_schedule_irq
+1 −1
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ ENTRY(clear_page)
ENTRY(__clear_user)
	!
	mov	#0, r0
	mov	#0xe0, r1	! 0xffffffe0
	mov	#0xffffffe0, r1
	!
	! r4..(r4+31)&~32 	   -------- not aligned	[ Area 0 ]
	! (r4+31)&~32..(r4+r5)&~32 -------- aligned	[ Area 1 ]