Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit fe9c2564 authored Aug 19, 2013 by Hans Verkuil Committed by Mauro Carvalho Chehab Aug 24, 2013

[media] adv7604/ad9389b/ths8200: decrease min_pixelclock to 25MHz

The CEA-861 standard allows for the 640x480 format at 25.175 MHz.
Ensure that that's allowed according to the struct v4l2_bt_timings_cap.

Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>

parent ef1ed8f5

drivers/media/i2c/ad9389b.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -631,7 +631,7 @@ static const struct v4l2_dv_timings_cap ad9389b_timings_cap = {
	.bt = {		.bt = {
	.max_width = 1920,		.max_width = 1920,
	.max_height = 1200,		.max_height = 1200,
	.min_pixelclock = 27000000,		.min_pixelclock = 25000000,
	.max_pixelclock = 170000000,		.max_pixelclock = 170000000,
	.standards = V4L2_DV_BT_STD_CEA861 \| V4L2_DV_BT_STD_DMT \|		.standards = V4L2_DV_BT_STD_CEA861 \| V4L2_DV_BT_STD_DMT \|
	V4L2_DV_BT_STD_GTF \| V4L2_DV_BT_STD_CVT,		V4L2_DV_BT_STD_GTF \| V4L2_DV_BT_STD_CVT,

drivers/media/i2c/adv7604.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -1162,7 +1162,7 @@ static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
	cap->type = V4L2_DV_BT_656_1120;		cap->type = V4L2_DV_BT_656_1120;
	cap->bt.max_width = 1920;		cap->bt.max_width = 1920;
	cap->bt.max_height = 1200;		cap->bt.max_height = 1200;
	cap->bt.min_pixelclock = 27000000;		cap->bt.min_pixelclock = 25000000;
	if (DIGITAL_INPUT)		if (DIGITAL_INPUT)
	cap->bt.max_pixelclock = 225000000;		cap->bt.max_pixelclock = 225000000;
	else		else

drivers/media/i2c/ths8200.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -49,7 +49,7 @@ static const struct v4l2_dv_timings_cap ths8200_timings_cap = {
	.bt = {		.bt = {
	.max_width = 1920,		.max_width = 1920,
	.max_height = 1080,		.max_height = 1080,
	.min_pixelclock = 27000000,		.min_pixelclock = 25000000,
	.max_pixelclock = 148500000,		.max_pixelclock = 148500000,
	.standards = V4L2_DV_BT_STD_CEA861,		.standards = V4L2_DV_BT_STD_CEA861,
	.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE,		.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE,