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Commit fd8f507c authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc. 



The PIPE_FRMCOUNT_GM45 and PIPE_FLIPCOUNT_GM45 names have bothered me
for a long time. The work equally well for ELK and onwards, so let's
s/GM45/G4X/.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b51a2842

drivers/gpu/drm/i915/i915_irq.c

+3 −3
Original line number Diff line number Diff line
@@ -710,10 +710,10 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 
	return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;

}



static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)

static u32 g4x_get_vblank_counter(struct drm_device *dev, int pipe)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int reg = PIPE_FRMCOUNT_GM45(pipe);

	int reg = PIPE_FRMCOUNT_G4X(pipe);



	return I915_READ(reg);

}
@@ -4400,7 +4400,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) 
		dev->driver->get_vblank_counter = i8xx_get_vblank_counter;

	} else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {

		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */

		dev->driver->get_vblank_counter = gm45_get_vblank_counter;

		dev->driver->get_vblank_counter = g4x_get_vblank_counter;

	} else {

		dev->driver->get_vblank_counter = i915_get_vblank_counter;

		dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */

drivers/gpu/drm/i915/i915_reg.h

+6 −6
Original line number Diff line number Diff line
@@ -4846,10 +4846,10 @@ enum skl_disp_power_wells { 
#define   PIPE_PIXEL_MASK         0x00ffffff

#define   PIPE_PIXEL_SHIFT        0

/* GM45+ just has to be different */

#define _PIPEA_FRMCOUNT_GM45	0x70040

#define _PIPEA_FLIPCOUNT_GM45	0x70044

#define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45)

#define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45)

#define _PIPEA_FRMCOUNT_G4X	0x70040

#define _PIPEA_FLIPCOUNT_G4X	0x70044

#define PIPE_FRMCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)

#define PIPE_FLIPCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)



/* Cursor A & B regs */

#define _CURACNTR		0x70080
@@ -5012,8 +5012,8 @@ enum skl_disp_power_wells { 
#define _PIPEBSTAT		(dev_priv->info.display_mmio_offset + 0x71024)

#define _PIPEBFRAMEHIGH		0x71040

#define _PIPEBFRAMEPIXEL	0x71044

#define _PIPEB_FRMCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x71040)

#define _PIPEB_FLIPCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x71044)

#define _PIPEB_FRMCOUNT_G4X	(dev_priv->info.display_mmio_offset + 0x71040)

#define _PIPEB_FLIPCOUNT_G4X	(dev_priv->info.display_mmio_offset + 0x71044)





/* Display B control */

drivers/gpu/drm/i915/intel_display.c

+2 −2
Original line number Diff line number Diff line
@@ -10822,7 +10822,7 @@ static bool page_flip_finished(struct intel_crtc *crtc) 
	 */

	return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==

		crtc->unpin_work->gtt_offset &&

		g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),

		g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),

				    crtc->unpin_work->flip_count);

}
@@ -11434,7 +11434,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, 
	intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);



	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))

		work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;

		work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;



	if (IS_VALLEYVIEW(dev)) {

		ring = &dev_priv->ring[BCS];