Loading arch/arm64/boot/dts/qcom/sa8155-adp-alcor.dtsi +38 −0 Original line number Diff line number Diff line Loading @@ -12,3 +12,41 @@ #include "sa8155-adp-common.dtsi" #include "sa8155-adp-alcor-display.dtsi" &pcie1 { qcom,boot-option = <0x0>; }; &pcie_rc1 { aqc_x4: aquantia,aqc107@pcie_rc1 { reg = <0 0 0 0 0>; compatible = "aquantia,aqc-107"; pci-ids = "1d6a:0001", "1d6a:d107", "1d6a:07b1", "1d6a:87b1", "1d6a:d108", "1d6a:08b1", "1d6a:88b1", "1d6a:d109", "1d6a:09b1", "1d6a:89b1", "1d6a:d100", "1d6a:00b1", "1d6a:80b1", "1d6a:11b1", "1d6a:91b1", "1d6a:51b1", "1d6a:12b1", "1d6a:92b1", "1d6a:52b1"; qcom,smmu; qcom,smmu-iova-base = /bits/ 64 <0x20000000>; qcom,smmu-iova-size = /bits/ 64 <0x40000000>; qcom,smmu-attr-atomic; qcom,smmu-attr-s1-bypass; }; }; Loading
arch/arm64/boot/dts/qcom/sa8155-adp-alcor.dtsi +38 −0 Original line number Diff line number Diff line Loading @@ -12,3 +12,41 @@ #include "sa8155-adp-common.dtsi" #include "sa8155-adp-alcor-display.dtsi" &pcie1 { qcom,boot-option = <0x0>; }; &pcie_rc1 { aqc_x4: aquantia,aqc107@pcie_rc1 { reg = <0 0 0 0 0>; compatible = "aquantia,aqc-107"; pci-ids = "1d6a:0001", "1d6a:d107", "1d6a:07b1", "1d6a:87b1", "1d6a:d108", "1d6a:08b1", "1d6a:88b1", "1d6a:d109", "1d6a:09b1", "1d6a:89b1", "1d6a:d100", "1d6a:00b1", "1d6a:80b1", "1d6a:11b1", "1d6a:91b1", "1d6a:51b1", "1d6a:12b1", "1d6a:92b1", "1d6a:52b1"; qcom,smmu; qcom,smmu-iova-base = /bits/ 64 <0x20000000>; qcom,smmu-iova-size = /bits/ 64 <0x40000000>; qcom,smmu-attr-atomic; qcom,smmu-attr-s1-bypass; }; };