Merge tag 'drm-intel-fixes-2016-05-02' of git://anongit.freedesktop.org/drm-intel into drm-fixes (fca09716) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/gpu/drm/i915/i915_drv.c

+31 −1

Original line number	Diff line number	Diff line
		@@ -792,7 +792,7 @@ static int i915_drm_resume(struct drm_device *dev)
		static int i915_drm_resume_early(struct drm_device *dev)
		{
		struct drm_i915_private *dev_priv = dev->dev_private;
		int ret = 0;
		int ret;

		/*
		* We have a resume ordering issue with the snd-hda driver also
		@@ -803,6 +803,36 @@ static int i915_drm_resume_early(struct drm_device *dev)
		* FIXME: This should be solved with a special hdmi sink device or
		* similar so that power domains can be employed.
		*/

		/*
		* Note that we need to set the power state explicitly, since we
		* powered off the device during freeze and the PCI core won't power
		* it back up for us during thaw. Powering off the device during
		* freeze is not a hard requirement though, and during the
		* suspend/resume phases the PCI core makes sure we get here with the
		* device powered on. So in case we change our freeze logic and keep
		* the device powered we can also remove the following set power state
		* call.
		*/
		ret = pci_set_power_state(dev->pdev, PCI_D0);
		if (ret) {
		DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
		goto out;
		}

		/*
		* Note that pci_enable_device() first enables any parent bridge
		* device and only then sets the power state for this device. The
		* bridge enabling is a nop though, since bridge devices are resumed
		* first. The order of enabling power and enabling the device is
		* imposed by the PCI core as described above, so here we preserve the
		* same order for the freeze/thaw phases.
		*
		* TODO: eventually we should remove pci_disable_device() /
		* pci_enable_enable_device() from suspend/resume. Due to how they
		* depend on the device enable refcount we can't anyway depend on them
		* disabling/enabling the device.
		*/
		if (pci_enable_device(dev->pdev)) {
		ret = -EIO;
		goto out;

drivers/gpu/drm/i915/i915_reg.h

+8 −1

Original line number	Diff line number	Diff line
		@@ -2907,7 +2907,14 @@ enum skl_disp_power_wells {
		#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
		#define BXT_RP_STATE_CAP _MMIO(0x138170)

		#define INTERVAL_1_28_US(us) (((us) * 100) >> 7)
		/*
		* Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
		* 8300) freezing up around GPU hangs. Looks as if even
		* scheduling/timer interrupts start misbehaving if the RPS
		* EI/thresholds are "bad", leading to a very sluggish or even
		* frozen machine.
		*/
		#define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
		#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
		#define INTERVAL_0_833_US(us) (((us) * 6) / 5)
		#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \

drivers/gpu/drm/i915/intel_ddi.c

+13 −9

Original line number	Diff line number	Diff line
		@@ -443,9 +443,17 @@ void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
		} else if (IS_BROADWELL(dev_priv)) {
		ddi_translations_fdi = bdw_ddi_translations_fdi;
		ddi_translations_dp = bdw_ddi_translations_dp;

		if (dev_priv->edp_low_vswing) {
		ddi_translations_edp = bdw_ddi_translations_edp;
		ddi_translations_hdmi = bdw_ddi_translations_hdmi;
		n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
		} else {
		ddi_translations_edp = bdw_ddi_translations_dp;
		n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
		}

		ddi_translations_hdmi = bdw_ddi_translations_hdmi;

		n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
		n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
		hdmi_default_entry = 7;
		@@ -3201,12 +3209,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
		intel_ddi_clock_get(encoder, pipe_config);
		}

		static void intel_ddi_destroy(struct drm_encoder *encoder)
		{
		/* HDMI has nothing special to destroy, so we can go with this. */
		intel_dp_encoder_destroy(encoder);
		}

		static bool intel_ddi_compute_config(struct intel_encoder *encoder,
		struct intel_crtc_state *pipe_config)
		{
		@@ -3225,7 +3227,8 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder,
		}

		static const struct drm_encoder_funcs intel_ddi_funcs = {
		.destroy = intel_ddi_destroy,
		.reset = intel_dp_encoder_reset,
		.destroy = intel_dp_encoder_destroy,
		};

		static struct intel_connector *
		@@ -3324,6 +3327,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
		intel_encoder->post_disable = intel_ddi_post_disable;
		intel_encoder->get_hw_state = intel_ddi_get_hw_state;
		intel_encoder->get_config = intel_ddi_get_config;
		intel_encoder->suspend = intel_dp_encoder_suspend;

		intel_dig_port->port = port;
		intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &

drivers/gpu/drm/i915/intel_display.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -13351,6 +13351,9 @@ static int intel_atomic_prepare_commit(struct drm_device *dev,
		}

		for_each_crtc_in_state(state, crtc, crtc_state, i) {
		if (state->legacy_cursor_update)
		continue;

		ret = intel_crtc_wait_for_pending_flips(crtc);
		if (ret)
		return ret;

drivers/gpu/drm/i915/intel_dp.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -4898,7 +4898,7 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder)
		kfree(intel_dig_port);
		}

		static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
		void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
		{
		struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);

		@@ -4940,7 +4940,7 @@ static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
		edp_panel_vdd_schedule_off(intel_dp);
		}

		static void intel_dp_encoder_reset(struct drm_encoder *encoder)
		void intel_dp_encoder_reset(struct drm_encoder *encoder)
		{
		struct intel_dp *intel_dp;