clk: qcom: Add GCC and SCC QUPv3 clocks for virtual clock (fc90a1a0) · Commits · e / devices / android_kernel_oneplus_sm8150

Documentation/devicetree/bindings/clock/qcom,virt.txt

+5 −3

Original line number	Diff line number	Diff line
		Qualcomm Technologies, Inc. Virtual Clocks

		Required properties:
		- compatible: Shall contain:
		"qcom,virt-clk-sm8150".
		- compatible: Shall contain one of the following:
		"qcom,virt-clk-sm8150-gcc",
		"qcom,virt-clk-sm8150-scc".

		- #clock-cells: Shall contain 1.
		- #reset-cells: Shall contain 1.

		Example:
		qcom,virtclk {
		compatible = "qcom,virt-clk-sm8150";
		compatible = "qcom,virt-clk-sm8150-gcc";
		#clock-cells = <1>;
		#reset-cells = <1>;
		};

drivers/clk/qcom/clk-virt.c

+273 −9

Original line number	Diff line number	Diff line
		@@ -24,6 +24,7 @@
		#include <linux/delay.h>
		#include <linux/habmm.h>
		#include <dt-bindings/clock/qcom,gcc-sm8150.h>
		#include <dt-bindings/clock/qcom,scc-sm8150.h>

		enum virtclk_cmd {
		CLK_MSG_GETID = 1,
		@@ -559,13 +560,13 @@ static int virtrc_reset_deassert(struct reset_controller_dev *rcdev,
		return __virtrc_reset(rcdev, id, 0);
		}

		struct reset_control_ops virtrc_ops = {
		static const struct reset_control_ops virtrc_ops = {
		.reset = virtrc_reset,
		.assert = virtrc_reset_assert,
		.deassert = virtrc_reset_deassert,
		};

		static struct virt_reset_map sm8150_virt_resets[] = {
		static struct virt_reset_map sm8150_gcc_virt_resets[] = {
		[GCC_QUSB2PHY_PRIM_BCR] = { "gcc_qusb2phy_prim_bcr" },
		[GCC_QUSB2PHY_SEC_BCR] = { "gcc_qusb2phy_sec_bcr" },
		[GCC_USB3_PHY_PRIM_BCR] = { "gcc_usb3_phy_prim_bcr" },
		@@ -583,6 +584,181 @@ static struct clk_virt gcc_qupv3_wrap0_s0_clk = {
		},
		};

		static struct clk_virt gcc_qupv3_wrap0_s1_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap0_s1_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap0_s2_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap0_s2_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap0_s3_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap0_s3_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap0_s4_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap0_s4_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap0_s5_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap0_s5_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap0_s6_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap0_s6_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap0_s7_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap0_s7_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap1_s0_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap1_s0_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap1_s1_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap1_s1_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap1_s2_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap1_s2_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap1_s3_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap1_s3_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap1_s4_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap1_s4_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap1_s5_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap1_s5_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap2_s0_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap2_s0_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap2_s1_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap2_s1_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap2_s2_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap2_s2_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap2_s3_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap2_s3_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap2_s4_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap2_s4_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap2_s5_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap2_s5_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap_0_m_ahb_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap_0_m_ahb_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap_0_s_ahb_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap_0_s_ahb_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap_1_m_ahb_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap_1_m_ahb_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap_1_s_ahb_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap_1_s_ahb_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap_2_m_ahb_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap_2_m_ahb_clk",
		},
		};

		static struct clk_virt gcc_qupv3_wrap_2_s_ahb_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_qupv3_wrap_2_s_ahb_clk",
		},
		};

		static struct clk_virt gcc_usb30_prim_master_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		@@ -709,8 +885,33 @@ static struct clk_virt gcc_usb3_sec_phy_com_aux_clk = {
		},
		};

		static struct clk_hw *sm8150_virt_clocks[] = {
		static struct clk_hw *sm8150_gcc_virt_clocks[] = {
		[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.hw,
		[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.hw,
		[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.hw,
		[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.hw,
		[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.hw,
		[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.hw,
		[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.hw,
		[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.hw,
		[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.hw,
		[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.hw,
		[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.hw,
		[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.hw,
		[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.hw,
		[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.hw,
		[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.hw,
		[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.hw,
		[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.hw,
		[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.hw,
		[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.hw,
		[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.hw,
		[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.hw,
		[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.hw,
		[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.hw,
		[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.hw,
		[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.hw,
		[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.hw,
		[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.hw,
		[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.hw,
		[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.hw,
		@@ -731,15 +932,78 @@ static struct clk_hw *sm8150_virt_clocks[] = {
		[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.hw,
		};

		static const struct clk_virt_desc clk_virt_sm8150 = {
		.clks = sm8150_virt_clocks,
		.num_clks = ARRAY_SIZE(sm8150_virt_clocks),
		.resets = sm8150_virt_resets,
		.num_resets = ARRAY_SIZE(sm8150_virt_resets),
		static const struct clk_virt_desc clk_virt_sm8150_gcc = {
		.clks = sm8150_gcc_virt_clocks,
		.num_clks = ARRAY_SIZE(sm8150_gcc_virt_clocks),
		.resets = sm8150_gcc_virt_resets,
		.num_resets = ARRAY_SIZE(sm8150_gcc_virt_resets),
		};

		static struct clk_virt scc_qupv3_se0_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "scc_qupv3_se0_clk",
		},
		};

		static struct clk_virt scc_qupv3_se1_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "scc_qupv3_se1_clk",
		},
		};

		static struct clk_virt scc_qupv3_se2_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "scc_qupv3_se2_clk",
		},
		};

		static struct clk_virt scc_qupv3_se3_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "scc_qupv3_se3_clk",
		},
		};

		static struct clk_virt scc_qupv3_m_hclk_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "scc_qupv3_m_hclk_clk",
		},
		};

		static struct clk_virt scc_qupv3_s_hclk_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "scc_qupv3_s_hclk_clk",
		},
		};

		static struct clk_hw *sm8150_scc_virt_clocks[] = {
		[SCC_QUPV3_SE0_CLK] = &scc_qupv3_se0_clk.hw,
		[SCC_QUPV3_SE1_CLK] = &scc_qupv3_se1_clk.hw,
		[SCC_QUPV3_SE2_CLK] = &scc_qupv3_se2_clk.hw,
		[SCC_QUPV3_SE3_CLK] = &scc_qupv3_se3_clk.hw,
		[SCC_QUPV3_M_HCLK_CLK] = &scc_qupv3_m_hclk_clk.hw,
		[SCC_QUPV3_S_HCLK_CLK] = &scc_qupv3_s_hclk_clk.hw,
		};

		static const struct clk_virt_desc clk_virt_sm8150_scc = {
		.clks = sm8150_scc_virt_clocks,
		.num_clks = ARRAY_SIZE(sm8150_scc_virt_clocks),
		};

		static const struct of_device_id clk_virt_match_table[] = {
		{ .compatible = "qcom,virt-clk-sm8150", .data = &clk_virt_sm8150},
		{
		.compatible = "qcom,virt-clk-sm8150-gcc",
		.data = &clk_virt_sm8150_gcc
		},
		{
		.compatible = "qcom,virt-clk-sm8150-scc",
		.data = &clk_virt_sm8150_scc
		},
		{ }
		};
		MODULE_DEVICE_TABLE(of, clk_virt_match_table);