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Commit fc908b0f authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: dispcc-sdm855: register byte0/1 divider clocks"

parents 9b5c639b 3ff7bdd1

drivers/clk/qcom/dispcc-sdm855.c

+2 −0
Original line number Diff line number Diff line
@@ -1387,9 +1387,11 @@ static struct clk_regmap *disp_cc_sdm855_clocks[] = { 
	[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,

	[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,

	[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,

	[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,

	[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,

	[DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,

	[DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,

	[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,

	[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,

	[DISP_CC_MDSS_DP_AUX1_CLK] = &disp_cc_mdss_dp_aux1_clk.clkr,

	[DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr,

include/dt-bindings/clock/qcom,dispcc-sdm855.h

+56 −54
Original line number Diff line number Diff line
@@ -18,60 +18,62 @@ 
#define DISP_CC_MDSS_AHB_CLK_SRC				1

#define DISP_CC_MDSS_BYTE0_CLK					2

#define DISP_CC_MDSS_BYTE0_CLK_SRC				3

#define DISP_CC_MDSS_BYTE0_INTF_CLK				4

#define DISP_CC_MDSS_BYTE1_CLK					5

#define DISP_CC_MDSS_BYTE1_CLK_SRC				6

#define DISP_CC_MDSS_BYTE1_INTF_CLK				7

#define DISP_CC_MDSS_DP_AUX1_CLK				8

#define DISP_CC_MDSS_DP_AUX1_CLK_SRC				9

#define DISP_CC_MDSS_DP_AUX_CLK					10

#define DISP_CC_MDSS_DP_AUX_CLK_SRC				11

#define DISP_CC_MDSS_DP_CRYPTO1_CLK				12

#define DISP_CC_MDSS_DP_CRYPTO1_CLK_SRC				13

#define DISP_CC_MDSS_DP_CRYPTO_CLK				14

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				15

#define DISP_CC_MDSS_DP_LINK1_CLK				16

#define DISP_CC_MDSS_DP_LINK1_CLK_SRC				17

#define DISP_CC_MDSS_DP_LINK1_INTF_CLK				18

#define DISP_CC_MDSS_DP_LINK_CLK				19

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				20

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				21

#define DISP_CC_MDSS_DP_PIXEL1_CLK				22

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				23

#define DISP_CC_MDSS_DP_PIXEL2_CLK				24

#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC				25

#define DISP_CC_MDSS_DP_PIXEL_CLK				26

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				27

#define DISP_CC_MDSS_EDP_AUX_CLK				28

#define DISP_CC_MDSS_EDP_AUX_CLK_SRC				29

#define DISP_CC_MDSS_EDP_GTC_CLK				30

#define DISP_CC_MDSS_EDP_GTC_CLK_SRC				31

#define DISP_CC_MDSS_EDP_LINK_CLK				32

#define DISP_CC_MDSS_EDP_LINK_CLK_SRC				33

#define DISP_CC_MDSS_EDP_LINK_INTF_CLK				34

#define DISP_CC_MDSS_EDP_PIXEL_CLK				35

#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC				36

#define DISP_CC_MDSS_ESC0_CLK					37

#define DISP_CC_MDSS_ESC0_CLK_SRC				38

#define DISP_CC_MDSS_ESC1_CLK					39

#define DISP_CC_MDSS_ESC1_CLK_SRC				40

#define DISP_CC_MDSS_MDP_CLK					41

#define DISP_CC_MDSS_MDP_CLK_SRC				42

#define DISP_CC_MDSS_MDP_LUT_CLK				43

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				44

#define DISP_CC_MDSS_PCLK0_CLK					45

#define DISP_CC_MDSS_PCLK0_CLK_SRC				46

#define DISP_CC_MDSS_PCLK1_CLK					47

#define DISP_CC_MDSS_PCLK1_CLK_SRC				48

#define DISP_CC_MDSS_ROT_CLK					49

#define DISP_CC_MDSS_ROT_CLK_SRC				50

#define DISP_CC_MDSS_RSCC_AHB_CLK				51

#define DISP_CC_MDSS_RSCC_VSYNC_CLK				52

#define DISP_CC_MDSS_VSYNC_CLK					53

#define DISP_CC_MDSS_VSYNC_CLK_SRC				54

#define DISP_CC_PLL0						55

#define DISP_CC_PLL1						56

#define DISP_CC_XO_CLK						57

#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				4

#define DISP_CC_MDSS_BYTE0_INTF_CLK				5

#define DISP_CC_MDSS_BYTE1_CLK					6

#define DISP_CC_MDSS_BYTE1_CLK_SRC				7

#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				8

#define DISP_CC_MDSS_BYTE1_INTF_CLK				9

#define DISP_CC_MDSS_DP_AUX1_CLK				10

#define DISP_CC_MDSS_DP_AUX1_CLK_SRC				11

#define DISP_CC_MDSS_DP_AUX_CLK					12

#define DISP_CC_MDSS_DP_AUX_CLK_SRC				13

#define DISP_CC_MDSS_DP_CRYPTO1_CLK				14

#define DISP_CC_MDSS_DP_CRYPTO1_CLK_SRC				15

#define DISP_CC_MDSS_DP_CRYPTO_CLK				16

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				17

#define DISP_CC_MDSS_DP_LINK1_CLK				18

#define DISP_CC_MDSS_DP_LINK1_CLK_SRC				19

#define DISP_CC_MDSS_DP_LINK1_INTF_CLK				20

#define DISP_CC_MDSS_DP_LINK_CLK				21

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				22

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				23

#define DISP_CC_MDSS_DP_PIXEL1_CLK				24

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				25

#define DISP_CC_MDSS_DP_PIXEL2_CLK				26

#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC				27

#define DISP_CC_MDSS_DP_PIXEL_CLK				28

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				29

#define DISP_CC_MDSS_EDP_AUX_CLK				30

#define DISP_CC_MDSS_EDP_AUX_CLK_SRC				31

#define DISP_CC_MDSS_EDP_GTC_CLK				32

#define DISP_CC_MDSS_EDP_GTC_CLK_SRC				33

#define DISP_CC_MDSS_EDP_LINK_CLK				34

#define DISP_CC_MDSS_EDP_LINK_CLK_SRC				35

#define DISP_CC_MDSS_EDP_LINK_INTF_CLK				36

#define DISP_CC_MDSS_EDP_PIXEL_CLK				37

#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC				38

#define DISP_CC_MDSS_ESC0_CLK					39

#define DISP_CC_MDSS_ESC0_CLK_SRC				40

#define DISP_CC_MDSS_ESC1_CLK					41

#define DISP_CC_MDSS_ESC1_CLK_SRC				42

#define DISP_CC_MDSS_MDP_CLK					43

#define DISP_CC_MDSS_MDP_CLK_SRC				44

#define DISP_CC_MDSS_MDP_LUT_CLK				45

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				46

#define DISP_CC_MDSS_PCLK0_CLK					47

#define DISP_CC_MDSS_PCLK0_CLK_SRC				48

#define DISP_CC_MDSS_PCLK1_CLK					49

#define DISP_CC_MDSS_PCLK1_CLK_SRC				50

#define DISP_CC_MDSS_ROT_CLK					51

#define DISP_CC_MDSS_ROT_CLK_SRC				52

#define DISP_CC_MDSS_RSCC_AHB_CLK				53

#define DISP_CC_MDSS_RSCC_VSYNC_CLK				54

#define DISP_CC_MDSS_VSYNC_CLK					55

#define DISP_CC_MDSS_VSYNC_CLK_SRC				56

#define DISP_CC_PLL0						57

#define DISP_CC_PLL1						58

#define DISP_CC_XO_CLK						59



#define DISP_CC_MDSS_CORE_BCR					0

#define DISP_CC_MDSS_RSCC_BCR					1