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Commit fc898bf5 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: add entry for mnoc ports and axi bus width for Trinket"

parents 98ef65e5 3c5589ee

Documentation/devicetree/bindings/display/msm/sde.txt

+2 −0
Original line number Diff line number Diff line
@@ -443,6 +443,8 @@ Optional properties: 
				ordering block

				0: lower priority pipe has to be on the left for a given pair of pipes.

				1: priority have to be explicitly configured for a given pair of pipes.

- qcom,sde-num-mnoc-ports:	A u32 property to indicate the number of mnoc ports

- qcom,sde-axi-bus-width:	A u32 property to indicate the axi bus width value in bytes



Bus Scaling Subnodes:

- qcom,sde-reg-bus:		Property to provide Bus scaling for register access for

arch/arm64/boot/dts/qcom/trinket-sde.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -182,6 +182,8 @@ 
		qcom,sde-reg-dma-trigger-off = <0x119c>;



		qcom,sde-secure-sid-mask = <0x0000401>;

		qcom,sde-num-mnoc-ports = <1>;

		qcom,sde-axi-bus-width = <16>;



		qcom,sde-sspp-vig-blocks {

			qcom,sde-vig-csc-off = <0x1a00>;

drivers/gpu/drm/msm/sde/sde_crtc.c

+4 −0
Original line number Diff line number Diff line
@@ -5714,6 +5714,10 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc, 
			catalog->perf.amortizable_threshold);

	sde_kms_info_add_keyint(info, "min_prefill_lines",

			catalog->perf.min_prefill_lines);

	sde_kms_info_add_keyint(info, "num_mnoc_ports",

			catalog->perf.num_mnoc_ports);

	sde_kms_info_add_keyint(info, "axi_bus_width",

			catalog->perf.axi_bus_width);

	sde_kms_info_add_keyint(info, "sec_ui_blendstage",

			catalog->sui_supported_blendstage);

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+18 −0
Original line number Diff line number Diff line
@@ -131,6 +131,8 @@ 
		"NV12/5/1/1.25 AB24/5/1/1.25 XB24/5/1/1.25"

#define DEFAULT_MAX_PER_PIPE_BW			2400000

#define DEFAULT_AMORTIZABLE_THRESHOLD		25

#define DEFAULT_MNOC_PORTS			2

#define DEFAULT_AXI_BUS_WIDTH			32

#define DEFAULT_CPU_MASK			0

#define DEFAULT_CPU_DMA_LATENCY			PM_QOS_DEFAULT_VALUE
@@ -204,6 +206,8 @@ enum { 
	PERF_CPU_DMA_LATENCY,

	PERF_QOS_LUT_MACROTILE_QSEED,

	PERF_SAFE_LUT_MACROTILE_QSEED,

	PERF_NUM_MNOC_PORTS,

	PERF_AXI_BUS_WIDTH,

	PERF_PROP_MAX,

};
@@ -506,6 +510,10 @@ static struct sde_prop_type sde_perf_prop[] = { 
			false, PROP_TYPE_U32_ARRAY},

	{PERF_SAFE_LUT_MACROTILE_QSEED, "qcom,sde-safe-lut-macrotile-qseed",

			false, PROP_TYPE_U32_ARRAY},

	{PERF_NUM_MNOC_PORTS, "qcom,sde-num-mnoc-ports",

			false, PROP_TYPE_U32},

	{PERF_AXI_BUS_WIDTH, "qcom,sde-axi-bus-width",

			false, PROP_TYPE_U32},

};



static struct sde_prop_type sspp_prop[] = {
@@ -3271,6 +3279,16 @@ static int sde_perf_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) 
			PROP_VALUE_ACCESS(prop_value,

					PERF_AMORTIZABLE_THRESHOLD, 0) :

			DEFAULT_AMORTIZABLE_THRESHOLD;

	cfg->perf.num_mnoc_ports =

			prop_exists[PERF_NUM_MNOC_PORTS] ?

			PROP_VALUE_ACCESS(prop_value,

				PERF_NUM_MNOC_PORTS, 0) :

			DEFAULT_MNOC_PORTS;

	cfg->perf.axi_bus_width =

			prop_exists[PERF_AXI_BUS_WIDTH] ?

			PROP_VALUE_ACCESS(prop_value,

				PERF_AXI_BUS_WIDTH, 0) :

			DEFAULT_AXI_BUS_WIDTH;



	if (prop_exists[PERF_DANGER_LUT] && prop_count[PERF_DANGER_LUT] <=

			SDE_QOS_LUT_USAGE_MAX) {

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+4 −0
Original line number Diff line number Diff line
@@ -994,6 +994,8 @@ struct sde_perf_cdp_cfg { 
 * @cdp_cfg            cdp use case configurations

 * @cpu_mask:          pm_qos cpu mask value

 * @cpu_dma_latency:   pm_qos cpu dma latency value

 * @axi_bus_width:     axi bus width value in bytes

 * @num_mnoc_ports:    number of mnoc ports

 */

struct sde_perf_cfg {

	u32 max_bw_low;
@@ -1020,6 +1022,8 @@ struct sde_perf_cfg { 
	struct sde_perf_cdp_cfg cdp_cfg[SDE_PERF_CDP_USAGE_MAX];

	u32 cpu_mask;

	u32 cpu_dma_latency;

	u32 axi_bus_width;

	u32 num_mnoc_ports;

};



/**