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Commit fc66d21a authored by Ramandeep Trehan's avatar Ramandeep Trehan
Browse files

ARM64: dts: msm: add inline crypto engine node 



Add inline crypto engine node to support hardware encryption.

Change-Id: I9f42aab0ddcd15358e66830b35b2336fd14fcba1
Signed-off-by: default avatarRamandeep Trehan <rtrehan@codeaurora.org>
parent ccc4db28

arch/arm64/boot/dts/qcom/trinket.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -890,6 +890,29 @@ 
		poll-delay-ms = <5000>;

	};



	ufs_ice: ufsice@4810000 {

		compatible = "qcom,ice";

		reg = <0x4810000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ufs_core_clk", "bus_clk",

				"iface_clk", "ice_core_clk";

		clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>,

			 <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,

			 <&clock_gcc GCC_UFS_PHY_AHB_CLK>,

			 <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>;

		qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;

		vdd-hba-supply = <&ufs_phy_gdsc>;

		qcom,msm-bus,name = "ufs_ice_noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<1 650 0 0>,    /* No vote */

				<1 650 1000 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "ufs";

	};



	ufsphy_mem: ufsphy_mem@4807000 {

		reg = <0x4807000 0xdb8>; /* PHY regs */

		reg-names = "phy_mem";
@@ -913,6 +936,7 @@ 
		interrupts = <0 356 0>;

		phys = <&ufsphy_mem>;

		phy-names = "ufsphy";

		ufs-qcom-crypto = <&ufs_ice>;



		lanes-per-direction = <1>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */