[PATCH] fbdev: framebuffer driver for Geode GX (fc4effc7) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/video/geode/Kconfig

+16 −1

Original line number	Diff line number	Diff line
		@@ -8,9 +8,24 @@ config FB_GEODE
		Say 'Y' here to allow you to select framebuffer drivers for
		the AMD Geode family of processors.

		config FB_GEODE_GX
		tristate "AMD Geode GX framebuffer support (EXPERIMENTAL)"
		depends on FB && FB_GEODE && EXPERIMENTAL
		select FB_CFB_FILLRECT
		select FB_CFB_COPYAREA
		select FB_CFB_IMAGEBLIT
		---help---
		Framebuffer driver for the display controller integrated into the
		AMD Geode GX processors.

		To compile this driver as a module, choose M here: the module will be
		called gxfb.

		If unsure, say N.

		config FB_GEODE_GX1
		tristate "AMD Geode GX1 framebuffer support (EXPERIMENTAL)"
		depends on FB_GEODE && EXPERIMENTAL
		depends on FB && FB_GEODE && EXPERIMENTAL
		select FB_CFB_FILLRECT
		select FB_CFB_COPYAREA
		select FB_CFB_IMAGEBLIT

drivers/video/geode/Makefile

+3 −1

Original line number	Diff line number	Diff line
		# Makefile for the Geode family framebuffer drivers

		obj-$(CONFIG_FB_GEODE_GX1) += gx1fb.o
		obj-$(CONFIG_FB_GEODE_GX) += gxfb.o

		gx1fb-objs := gx1fb_core.o display_gx1.o video_cs5530.o
		gxfb-objs := gxfb_core.o display_gx.o video_gx.o

drivers/video/geode/display_gx.c

0 → 100644

+156 −0

Original line number	Diff line number	Diff line
		/*
		* Geode GX display controller.
		*
		* Copyright (C) 2005 Arcom Control Systems Ltd.
		*
		* Portions from AMD's original 2.4 driver:
		* Copyright (C) 2004 Advanced Micro Devices, Inc.
		*
		* This program is free software; you can redistribute it and/or modify it
		* under the terms of the GNU General Public License as published by * the
		* Free Software Foundation; either version 2 of the License, or * (at your
		* option) any later version.
		*/
		#include <linux/spinlock.h>
		#include <linux/fb.h>
		#include <linux/delay.h>
		#include <asm/io.h>
		#include <asm/div64.h>
		#include <asm/delay.h>

		#include "geodefb.h"
		#include "display_gx.h"

		int gx_frame_buffer_size(void)
		{
		/* Assuming 16 MiB. */
		return 1610241024;
		}

		int gx_line_delta(int xres, int bpp)
		{
		/* Must be a multiple of 8 bytes. */
		return (xres * (bpp >> 3) + 7) & ~0x7;
		}

		static void gx_set_mode(struct fb_info *info)
		{
		struct geodefb_par *par = info->par;
		u32 gcfg, dcfg;
		int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
		int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;

		/* Unlock the display controller registers. */
		readl(par->dc_regs + DC_UNLOCK);
		writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);

		gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
		dcfg = readl(par->dc_regs + DC_DISPLAY_CFG);

		/* Disable the timing generator. */
		dcfg &= ~(DC_DCFG_TGEN);
		writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);

		/* Wait for pending memory requests before disabling the FIFO load. */
		udelay(100);

		/* Disable FIFO load and compression. */
		gcfg &= ~(DC_GCFG_DFLE \| DC_GCFG_CMPE \| DC_GCFG_DECE);
		writel(gcfg, par->dc_regs + DC_GENERAL_CFG);

		/* Setup DCLK and its divisor. */
		par->vid_ops->set_dclk(info);

		/*
		* Setup new mode.
		*/

		/* Clear all unused feature bits. */
		gcfg &= DC_GCFG_YUVM \| DC_GCFG_VDSE;
		dcfg = 0;

		/* Set FIFO priority (default 6/5) and enable. */
		/* FIXME: increase fifo priority for 1280x1024 and higher modes? */
		gcfg \|= (6 << DC_GCFG_DFHPEL_POS) \| (5 << DC_GCFG_DFHPSL_POS) \| DC_GCFG_DFLE;

		/* Framebuffer start offset. */
		writel(0, par->dc_regs + DC_FB_ST_OFFSET);

		/* Line delta and line buffer length. */
		writel(info->fix.line_length >> 3, par->dc_regs + DC_GFX_PITCH);
		writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,
		par->dc_regs + DC_LINE_SIZE);

		/* Enable graphics and video data and unmask address lines. */
		dcfg \|= DC_DCFG_GDEN \| DC_DCFG_VDEN \| DC_DCFG_A20M \| DC_DCFG_A18M;

		/* Set pixel format. */
		switch (info->var.bits_per_pixel) {
		case 8:
		dcfg \|= DC_DCFG_DISP_MODE_8BPP;
		break;
		case 16:
		dcfg \|= DC_DCFG_DISP_MODE_16BPP;
		dcfg \|= DC_DCFG_16BPP_MODE_565;
		break;
		case 32:
		dcfg \|= DC_DCFG_DISP_MODE_24BPP;
		dcfg \|= DC_DCFG_PALB;
		break;
		}

		/* Enable timing generator. */
		dcfg \|= DC_DCFG_TGEN;

		/* Horizontal and vertical timings. */
		hactive = info->var.xres;
		hblankstart = hactive;
		hsyncstart = hblankstart + info->var.right_margin;
		hsyncend = hsyncstart + info->var.hsync_len;
		hblankend = hsyncend + info->var.left_margin;
		htotal = hblankend;

		vactive = info->var.yres;
		vblankstart = vactive;
		vsyncstart = vblankstart + info->var.lower_margin;
		vsyncend = vsyncstart + info->var.vsync_len;
		vblankend = vsyncend + info->var.upper_margin;
		vtotal = vblankend;

		writel((hactive - 1) \| ((htotal - 1) << 16), par->dc_regs + DC_H_ACTIVE_TIMING);
		writel((hblankstart - 1) \| ((hblankend - 1) << 16), par->dc_regs + DC_H_BLANK_TIMING);
		writel((hsyncstart - 1) \| ((hsyncend - 1) << 16), par->dc_regs + DC_H_SYNC_TIMING);

		writel((vactive - 1) \| ((vtotal - 1) << 16), par->dc_regs + DC_V_ACTIVE_TIMING);
		writel((vblankstart - 1) \| ((vblankend - 1) << 16), par->dc_regs + DC_V_BLANK_TIMING);
		writel((vsyncstart - 1) \| ((vsyncend - 1) << 16), par->dc_regs + DC_V_SYNC_TIMING);

		/* Write final register values. */
		writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
		writel(gcfg, par->dc_regs + DC_GENERAL_CFG);

		par->vid_ops->configure_display(info);

		/* Relock display controller registers */
		writel(0, par->dc_regs + DC_UNLOCK);
		}

		static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
		unsigned red, unsigned green, unsigned blue)
		{
		struct geodefb_par *par = info->par;
		int val;

		/* Hardware palette is in RGB 8-8-8 format. */
		val = (red << 8) & 0xff0000;
		val \|= (green) & 0x00ff00;
		val \|= (blue >> 8) & 0x0000ff;

		writel(regno, par->dc_regs + DC_PAL_ADDRESS);
		writel(val, par->dc_regs + DC_PAL_DATA);
		}

		struct geode_dc_ops gx_dc_ops = {
		.set_mode = gx_set_mode,
		.set_palette_reg = gx_set_hw_palette_reg,
		};

drivers/video/geode/display_gx.h

0 → 100644

+96 −0

Original line number	Diff line number	Diff line
		/*
		* Geode GX display controller
		*
		* Copyright (C) 2006 Arcom Control Systems Ltd.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License as published by
		* the Free Software Foundation; either version 2 of the License, or
		* (at your option) any later version.
		*/
		#ifndef __DISPLAY_GX_H__
		#define __DISPLAY_GX_H__

		int gx_frame_buffer_size(void);
		int gx_line_delta(int xres, int bpp);

		extern struct geode_dc_ops gx_dc_ops;

		/* Display controller registers */

		#define DC_UNLOCK 0x00
		# define DC_UNLOCK_CODE 0x00004758

		#define DC_GENERAL_CFG 0x04
		# define DC_GCFG_DFLE 0x00000001
		# define DC_GCFG_CURE 0x00000002
		# define DC_GCFG_ICNE 0x00000004
		# define DC_GCFG_VIDE 0x00000008
		# define DC_GCFG_CMPE 0x00000020
		# define DC_GCFG_DECE 0x00000040
		# define DC_GCFG_VGAE 0x00000080
		# define DC_GCFG_DFHPSL_MASK 0x00000F00
		# define DC_GCFG_DFHPSL_POS 8
		# define DC_GCFG_DFHPEL_MASK 0x0000F000
		# define DC_GCFG_DFHPEL_POS 12
		# define DC_GCFG_STFM 0x00010000
		# define DC_GCFG_FDTY 0x00020000
		# define DC_GCFG_VGAFT 0x00040000
		# define DC_GCFG_VDSE 0x00080000
		# define DC_GCFG_YUVM 0x00100000
		# define DC_GCFG_VFSL 0x00800000
		# define DC_GCFG_SIGE 0x01000000
		# define DC_GCFG_SGRE 0x02000000
		# define DC_GCFG_SGFR 0x04000000
		# define DC_GCFG_CRC_MODE 0x08000000
		# define DC_GCFG_DIAG 0x10000000
		# define DC_GCFG_CFRW 0x20000000

		#define DC_DISPLAY_CFG 0x08
		# define DC_DCFG_TGEN 0x00000001
		# define DC_DCFG_GDEN 0x00000008
		# define DC_DCFG_VDEN 0x00000010
		# define DC_DCFG_TRUP 0x00000040
		# define DC_DCFG_DISP_MODE_MASK 0x00000300
		# define DC_DCFG_DISP_MODE_8BPP 0x00000000
		# define DC_DCFG_DISP_MODE_16BPP 0x00000100
		# define DC_DCFG_DISP_MODE_24BPP 0x00000200
		# define DC_DCFG_16BPP_MODE_MASK 0x00000c00
		# define DC_DCFG_16BPP_MODE_565 0x00000000
		# define DC_DCFG_16BPP_MODE_555 0x00000100
		# define DC_DCFG_16BPP_MODE_444 0x00000200
		# define DC_DCFG_DCEN 0x00080000
		# define DC_DCFG_PALB 0x02000000
		# define DC_DCFG_FRLK 0x04000000
		# define DC_DCFG_VISL 0x08000000
		# define DC_DCFG_FRSL 0x20000000
		# define DC_DCFG_A18M 0x40000000
		# define DC_DCFG_A20M 0x80000000

		#define DC_FB_ST_OFFSET 0x10

		#define DC_LINE_SIZE 0x30
		# define DC_LINE_SIZE_FB_LINE_SIZE_MASK 0x000007ff
		# define DC_LINE_SIZE_FB_LINE_SIZE_POS 0
		# define DC_LINE_SIZE_CB_LINE_SIZE_MASK 0x007f0000
		# define DC_LINE_SIZE_CB_LINE_SIZE_POS 16
		# define DC_LINE_SIZE_VID_LINE_SIZE_MASK 0xff000000
		# define DC_LINE_SIZE_VID_LINE_SIZE_POS 24

		#define DC_GFX_PITCH 0x34
		# define DC_GFX_PITCH_FB_PITCH_MASK 0x0000ffff
		# define DC_GFX_PITCH_FB_PITCH_POS 0
		# define DC_GFX_PITCH_CB_PITCH_MASK 0xffff0000
		# define DC_GFX_PITCH_CB_PITCH_POS 16

		#define DC_H_ACTIVE_TIMING 0x40
		#define DC_H_BLANK_TIMING 0x44
		#define DC_H_SYNC_TIMING 0x48
		#define DC_V_ACTIVE_TIMING 0x50
		#define DC_V_BLANK_TIMING 0x54
		#define DC_V_SYNC_TIMING 0x58

		#define DC_PAL_ADDRESS 0x70
		#define DC_PAL_DATA 0x74

		#endif /* !__DISPLAY_GX1_H__ */

drivers/video/geode/gxfb_core.c

0 → 100644

+423 −0

Original line number	Diff line number	Diff line
		/*
		* Geode GX framebuffer driver.
		*
		* Copyright (C) 2006 Arcom Control Systems Ltd.
		*
		* This program is free software; you can redistribute it and/or modify it
		* under the terms of the GNU General Public License as published by the
		* Free Software Foundation; either version 2 of the License, or (at your
		* option) any later version.
		*
		*
		* This driver assumes that the BIOS has created a virtual PCI device header
		* for the video device. The PCI header is assumed to contain the following
		* BARs:
		*
		* BAR0 - framebuffer memory
		* BAR1 - graphics processor registers
		* BAR2 - display controller registers
		* BAR3 - video processor and flat panel control registers.
		*
		* 16 MiB of framebuffer memory is assumed to be available.
		*/
		#include <linux/module.h>
		#include <linux/kernel.h>
		#include <linux/errno.h>
		#include <linux/string.h>
		#include <linux/mm.h>
		#include <linux/tty.h>
		#include <linux/slab.h>
		#include <linux/delay.h>
		#include <linux/fb.h>
		#include <linux/init.h>
		#include <linux/pci.h>

		#include "geodefb.h"
		#include "display_gx.h"
		#include "video_gx.h"

		static char mode_option[32] = "640x480-16@60";

		/* Modes relevant to the GX (taken from modedb.c) */
		static const struct fb_videomode __initdata gx_modedb[] = {
		/* 640x480-60 VESA */
		{ NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
		0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
		/* 640x480-75 VESA */
		{ NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
		0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
		/* 640x480-85 VESA */
		{ NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
		0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
		/* 800x600-60 VESA */
		{ NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
		FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
		FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
		/* 800x600-75 VESA */
		{ NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
		FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
		FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
		/* 800x600-85 VESA */
		{ NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
		FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
		FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
		/* 1024x768-60 VESA */
		{ NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
		0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
		/* 1024x768-75 VESA */
		{ NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
		FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
		FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
		/* 1024x768-85 VESA */
		{ NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
		FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
		FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
		/* 1280x960-60 VESA */
		{ NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
		FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
		FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
		/* 1280x960-85 VESA */
		{ NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
		FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
		FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
		/* 1280x1024-60 VESA */
		{ NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
		FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
		FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
		/* 1280x1024-75 VESA */
		{ NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
		FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
		FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
		/* 1280x1024-85 VESA */
		{ NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
		FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
		FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
		/* 1600x1200-60 VESA */
		{ NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
		FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
		FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
		/* 1600x1200-75 VESA */
		{ NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
		FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
		FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
		/* 1600x1200-85 VESA */
		{ NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
		FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
		FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
		};

		static int gxfb_check_var(struct fb_var_screeninfo var, struct fb_info info)
		{
		if (var->xres > 1600 \|\| var->yres > 1200)
		return -EINVAL;
		if ((var->xres > 1280 \|\| var->yres > 1024) && var->bits_per_pixel > 16)
		return -EINVAL;

		if (var->bits_per_pixel == 32) {
		var->red.offset = 16; var->red.length = 8;
		var->green.offset = 8; var->green.length = 8;
		var->blue.offset = 0; var->blue.length = 8;
		} else if (var->bits_per_pixel == 16) {
		var->red.offset = 11; var->red.length = 5;
		var->green.offset = 5; var->green.length = 6;
		var->blue.offset = 0; var->blue.length = 5;
		} else if (var->bits_per_pixel == 8) {
		var->red.offset = 0; var->red.length = 8;
		var->green.offset = 0; var->green.length = 8;
		var->blue.offset = 0; var->blue.length = 8;
		} else
		return -EINVAL;
		var->transp.offset = 0; var->transp.length = 0;

		/* Enough video memory? */
		if (gx_line_delta(var->xres, var->bits_per_pixel) * var->yres > info->fix.smem_len)
		return -EINVAL;

		/* FIXME: Check timing parameters here? */

		return 0;
		}

		static int gxfb_set_par(struct fb_info *info)
		{
		struct geodefb_par *par = info->par;

		if (info->var.bits_per_pixel > 8) {
		info->fix.visual = FB_VISUAL_TRUECOLOR;
		fb_dealloc_cmap(&info->cmap);
		} else {
		info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
		fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0);
		}

		info->fix.line_length = gx_line_delta(info->var.xres, info->var.bits_per_pixel);

		par->dc_ops->set_mode(info);

		return 0;
		}

		static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
		{
		chan &= 0xffff;
		chan >>= 16 - bf->length;
		return chan << bf->offset;
		}

		static int gxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
		unsigned blue, unsigned transp,
		struct fb_info *info)
		{
		struct geodefb_par *par = info->par;

		if (info->var.grayscale) {
		/* grayscale = 0.30R + 0.59G + 0.11B /
		red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
		}

		/* Truecolor has hardware independent palette */
		if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
		u32 *pal = info->pseudo_palette;
		u32 v;

		if (regno >= 16)
		return -EINVAL;

		v = chan_to_field(red, &info->var.red);
		v \|= chan_to_field(green, &info->var.green);
		v \|= chan_to_field(blue, &info->var.blue);

		pal[regno] = v;
		} else {
		if (regno >= 256)
		return -EINVAL;

		par->dc_ops->set_palette_reg(info, regno, red, green, blue);
		}

		return 0;
		}

		static int gxfb_blank(int blank_mode, struct fb_info *info)
		{
		struct geodefb_par *par = info->par;

		return par->vid_ops->blank_display(info, blank_mode);
		}

		static int __init gxfb_map_video_memory(struct fb_info info, struct pci_dev dev)
		{
		struct geodefb_par *par = info->par;
		int fb_len;
		int ret;

		ret = pci_enable_device(dev);
		if (ret < 0)
		return ret;

		ret = pci_request_region(dev, 3, "gxfb (video processor)");
		if (ret < 0)
		return ret;
		par->vid_regs = ioremap(pci_resource_start(dev, 3),
		pci_resource_len(dev, 3));
		if (!par->vid_regs)
		return -ENOMEM;

		ret = pci_request_region(dev, 2, "gxfb (display controller)");
		if (ret < 0)
		return ret;
		par->dc_regs = ioremap(pci_resource_start(dev, 2), pci_resource_len(dev, 2));
		if (!par->dc_regs)
		return -ENOMEM;

		ret = pci_request_region(dev, 0, "gxfb (framebuffer)");
		if (ret < 0)
		return ret;
		if ((fb_len = gx_frame_buffer_size()) < 0)
		return -ENOMEM;
		info->fix.smem_start = pci_resource_start(dev, 0);
		info->fix.smem_len = fb_len;
		info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
		if (!info->screen_base)
		return -ENOMEM;

		dev_info(&dev->dev, "%d Kibyte of video memory at 0x%lx\n",
		info->fix.smem_len / 1024, info->fix.smem_start);

		return 0;
		}

		static struct fb_ops gxfb_ops = {
		.owner = THIS_MODULE,
		.fb_check_var = gxfb_check_var,
		.fb_set_par = gxfb_set_par,
		.fb_setcolreg = gxfb_setcolreg,
		.fb_blank = gxfb_blank,
		/* No HW acceleration for now. */
		.fb_fillrect = cfb_fillrect,
		.fb_copyarea = cfb_copyarea,
		.fb_imageblit = cfb_imageblit,
		};

		static struct fb_info * __init gxfb_init_fbinfo(struct device *dev)
		{
		struct geodefb_par *par;
		struct fb_info *info;

		/* Alloc enough space for the pseudo palette. */
		info = framebuffer_alloc(sizeof(struct geodefb_par) + sizeof(u32) * 16, dev);
		if (!info)
		return NULL;

		par = info->par;

		strcpy(info->fix.id, "Geode GX");

		info->fix.type = FB_TYPE_PACKED_PIXELS;
		info->fix.type_aux = 0;
		info->fix.xpanstep = 0;
		info->fix.ypanstep = 0;
		info->fix.ywrapstep = 0;
		info->fix.accel = FB_ACCEL_NONE;

		info->var.nonstd = 0;
		info->var.activate = FB_ACTIVATE_NOW;
		info->var.height = -1;
		info->var.width = -1;
		info->var.accel_flags = 0;
		info->var.vmode = FB_VMODE_NONINTERLACED;

		info->fbops = &gxfb_ops;
		info->flags = FBINFO_DEFAULT;
		info->node = -1;

		info->pseudo_palette = (void *)par + sizeof(struct geodefb_par);

		info->var.grayscale = 0;

		return info;
		}

		static int __init gxfb_probe(struct pci_dev pdev, const struct pci_device_id id)
		{
		struct geodefb_par *par;
		struct fb_info *info;
		int ret;

		info = gxfb_init_fbinfo(&pdev->dev);
		if (!info)
		return -ENOMEM;
		par = info->par;

		/* GX display controller and GX video device. */
		par->dc_ops = &gx_dc_ops;
		par->vid_ops = &gx_vid_ops;

		if ((ret = gxfb_map_video_memory(info, pdev)) < 0) {
		dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n");
		goto err;
		}

		ret = fb_find_mode(&info->var, info, mode_option,
		gx_modedb, ARRAY_SIZE(gx_modedb), NULL, 16);
		if (ret == 0 \|\| ret == 4) {
		dev_err(&pdev->dev, "could not find valid video mode\n");
		ret = -EINVAL;
		goto err;
		}

		/* Clear the frame buffer of garbage. */
		memset_io(info->screen_base, 0, info->fix.smem_len);

		gxfb_check_var(&info->var, info);
		gxfb_set_par(info);

		if (register_framebuffer(info) < 0) {
		ret = -EINVAL;
		goto err;
		}
		pci_set_drvdata(pdev, info);
		printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id);
		return 0;

		err:
		if (info->screen_base) {
		iounmap(info->screen_base);
		pci_release_region(pdev, 0);
		}
		if (par->vid_regs) {
		iounmap(par->vid_regs);
		pci_release_region(pdev, 3);
		}
		if (par->dc_regs) {
		iounmap(par->dc_regs);
		pci_release_region(pdev, 2);
		}

		pci_disable_device(pdev);

		if (info)
		framebuffer_release(info);
		return ret;
		}

		static void gxfb_remove(struct pci_dev *pdev)
		{
		struct fb_info *info = pci_get_drvdata(pdev);
		struct geodefb_par *par = info->par;

		unregister_framebuffer(info);

		iounmap((void __iomem *)info->screen_base);
		pci_release_region(pdev, 0);

		iounmap(par->vid_regs);
		pci_release_region(pdev, 3);

		iounmap(par->dc_regs);
		pci_release_region(pdev, 2);

		pci_disable_device(pdev);
		pci_set_drvdata(pdev, NULL);

		framebuffer_release(info);
		}

		static struct pci_device_id gxfb_id_table[] = {
		{ PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_VIDEO,
		PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
		0xff0000, 0 },
		{ 0, }
		};

		MODULE_DEVICE_TABLE(pci, gxfb_id_table);

		static struct pci_driver gxfb_driver = {
		.name = "gxfb",
		.id_table = gxfb_id_table,
		.probe = gxfb_probe,
		.remove = gxfb_remove,
		};

		static int __init gxfb_init(void)
		{
		#ifndef MODULE
		if (fb_get_options("gxfb", NULL))
		return -ENODEV;
		#endif
		return pci_register_driver(&gxfb_driver);
		}

		static void __exit gxfb_cleanup(void)
		{
		pci_unregister_driver(&gxfb_driver);
		}

		module_init(gxfb_init);
		module_exit(gxfb_cleanup);

		module_param_string(mode, mode_option, sizeof(mode_option), 0444);
		MODULE_PARM_DESC(mode, "video mode (<x>x<y>[-<bpp>][@<refr>])");

		MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode GX");
		MODULE_LICENSE("GPL");