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Commit fbd4cc0e authored by Mark Yao's avatar Mark Yao Committed by Heiko Stuebner
Browse files

arm64: dts: rockchip: Add rk3399 vop and display-subsystem 



Add devicetree nodes for rk3399 VOP (Video Output Processors), and the
top level display-subsystem root node.

Later patches add endpoints (eDP, HDMI, MIPI, etc) that attach to the
VOPs' output ports.

Signed-off-by: default avatarMark Yao <mark.yao@rock-chips.com>
Signed-off-by: default avatarYakir Yang <ykk@rock-chips.com>
Signed-off-by: default avatarCaesar Wang <wxt@rock-chips.com>
Signed-off-by: default avatarJacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent bc911f25

arch/arm64/boot/dts/rockchip/rk3399.dtsi

+65 −0
Original line number Diff line number Diff line
@@ -160,6 +160,11 @@ 
		};

	};



	display-subsystem {

		compatible = "rockchip,display-subsystem";

		ports = <&vopl_out>, <&vopb_out>;

	};



	pmu_a53 {

		compatible = "arm,cortex-a53-pmu";

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
@@ -1443,6 +1448,66 @@ 
		status = "disabled";

	};



	vopl: vop@ff8f0000 {

		compatible = "rockchip,rk3399-vop-lit";

		reg = <0x0 0xff8f0000 0x0 0x3efc>;

		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;

		clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;

		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";

		iommus = <&vopl_mmu>;

		power-domains = <&power RK3399_PD_VOPL>;

		resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;

		reset-names = "axi", "ahb", "dclk";

		status = "disabled";



		vopl_out: port {

			#address-cells = <1>;

			#size-cells = <0>;

		};

	};



	vopl_mmu: iommu@ff8f3f00 {

		compatible = "rockchip,iommu";

		reg = <0x0 0xff8f3f00 0x0 0x100>;

		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;

		interrupt-names = "vopl_mmu";

		clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;

		clock-names = "aclk", "hclk";

		power-domains = <&power RK3399_PD_VOPL>;

		#iommu-cells = <0>;

		status = "disabled";

	};



	vopb: vop@ff900000 {

		compatible = "rockchip,rk3399-vop-big";

		reg = <0x0 0xff900000 0x0 0x3efc>;

		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;

		clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;

		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";

		iommus = <&vopb_mmu>;

		power-domains = <&power RK3399_PD_VOPB>;

		resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;

		reset-names = "axi", "ahb", "dclk";

		status = "disabled";



		vopb_out: port {

			#address-cells = <1>;

			#size-cells = <0>;

		};

	};



	vopb_mmu: iommu@ff903f00 {

		compatible = "rockchip,iommu";

		reg = <0x0 0xff903f00 0x0 0x100>;

		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;

		interrupt-names = "vopb_mmu";

		clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;

		clock-names = "aclk", "hclk";

		power-domains = <&power RK3399_PD_VOPB>;

		#iommu-cells = <0>;

		status = "disabled";

	};



	gpu: gpu@ff9a0000 {

		compatible = "rockchip,rk3399-mali", "arm,mali-t860";

		reg = <0x0 0xff9a0000 0x0 0x10000>;