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Commit faf9e01e authored by Alexander Beykun's avatar Alexander Beykun
Browse files

drm/msm/sde: Add ubwc 3.0 support 



Add ubwc 3.0 specific initialization sequence,
disable const color when ubwc 3.0 is set to ubwc 2.0
compatible mode, add dt node for macro tile mode.

Change-Id: I954b946c4e45baaf5cadbc69a6f2cc36291155fc
Signed-off-by: default avatarAlexander Beykun <abeykun@codeaurora.org>
parent 8d588f99

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+11 −1
Original line number Diff line number Diff line
@@ -58,6 +58,9 @@ 
/* default ubwc swizzle register value */

#define DEFAULT_SDE_UBWC_SWIZZLE 0x0



/* default ubwc macrotile mode value */

#define DEFAULT_SDE_UBWC_MACROTILE_MODE 0x0



/* default hardware block size if dtsi entry is not present */

#define DEFAULT_SDE_HW_BLOCK_LEN 0x100
@@ -150,6 +153,7 @@ enum sde_prop { 
	IDLE_PC,

	DEST_SCALER,

	SMART_PANEL_ALIGN_MODE,

	MACROTILE_MODE,

	SDE_PROP_MAX,

};
@@ -417,6 +421,7 @@ static struct sde_prop_type sde_prop[] = { 
	{DEST_SCALER, "qcom,sde-has-dest-scaler", false, PROP_TYPE_BOOL},

	{SMART_PANEL_ALIGN_MODE, "qcom,sde-smart-panel-align-mode",

			false, PROP_TYPE_U32},

	{MACROTILE_MODE, "qcom,sde-macrotile-mode", false, PROP_TYPE_U32},

};



static struct sde_prop_type sde_perf_prop[] = {
@@ -2871,10 +2876,15 @@ static int sde_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) 
	if (!prop_exists[BANK_BIT])

		cfg->mdp[0].highest_bank_bit = DEFAULT_SDE_HIGHEST_BANK_BIT;



	cfg->ubwc_version = PROP_VALUE_ACCESS(prop_value, UBWC_VERSION, 0);

	cfg->ubwc_version = SDE_HW_UBWC_VER(PROP_VALUE_ACCESS(prop_value,

			UBWC_VERSION, 0));

	if (!prop_exists[UBWC_VERSION])

		cfg->ubwc_version = DEFAULT_SDE_UBWC_VERSION;



	cfg->macrotile_mode = PROP_VALUE_ACCESS(prop_value, MACROTILE_MODE, 0);

	if (!prop_exists[MACROTILE_MODE])

		cfg->macrotile_mode = DEFAULT_SDE_UBWC_MACROTILE_MODE;



	cfg->mdp[0].ubwc_static = PROP_VALUE_ACCESS(prop_value, UBWC_STATIC, 0);

	if (!prop_exists[UBWC_STATIC])

		cfg->mdp[0].ubwc_static = DEFAULT_SDE_UBWC_STATIC;

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+12 −4
Original line number Diff line number Diff line
@@ -80,16 +80,22 @@ 
#define IS_SDE_CTL_REV_100(rev) \

	((rev) == SDE_CTL_CFG_VERSION_1_0_0)



#define SDE_HW_UBWC_VER(rev) \

	SDE_HW_VER((((rev) >> 8) & 0xF), (((rev) >> 4) & 0xF), ((rev) & 0xF))



/**

 * Supported UBWC feature versions

 */

enum {

	SDE_HW_UBWC_VER_10 = 0x100,

	SDE_HW_UBWC_VER_20 = 0x200,

	SDE_HW_UBWC_VER_30 = 0x300,

	SDE_HW_UBWC_VER_10 = SDE_HW_UBWC_VER(0x100),

	SDE_HW_UBWC_VER_20 = SDE_HW_UBWC_VER(0x200),

	SDE_HW_UBWC_VER_30 = SDE_HW_UBWC_VER(0x300),

};



#define IS_UBWC_20_SUPPORTED(rev)       ((rev) >= SDE_HW_UBWC_VER_20)

#define IS_UBWC_20_SUPPORTED(rev) \

		IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_UBWC_VER_20)

#define IS_UBWC_30_SUPPORTED(rev) \

		IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_UBWC_VER_30)



/**

 * MDP TOP BLOCK features
@@ -991,6 +997,7 @@ struct sde_perf_cfg { 
 * @wb_formats         Supported formats for wb

 * @vbif_qos_nlvl      number of vbif QoS priority level

 * @ts_prefill_rev     prefill traffic shaper feature revision

 * @macrotile_mode     UBWC parameter for macro tile channel distribution

 */

struct sde_mdss_cfg {

	u32 hwversion;
@@ -1014,6 +1021,7 @@ struct sde_mdss_cfg { 
	bool has_idle_pc;

	u32 vbif_qos_nlvl;

	u32 ts_prefill_rev;

	u32 macrotile_mode;



	bool has_hdr;

	u32 mdss_count;

drivers/gpu/drm/msm/sde/sde_hw_top.c

+20 −5
Original line number Diff line number Diff line 
/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -17,6 +17,7 @@ 
#include "sde_kms.h"



#define SSPP_SPARE                        0x28

#define UBWC_DEC_HW_VERSION               0x058

#define UBWC_STATIC                       0x144



#define FLD_SPLIT_DISPLAY_CMD             BIT(1)
@@ -340,17 +341,31 @@ static void sde_hw_setup_dce(struct sde_hw_mdp *mdp, u32 dce_sel) 
void sde_hw_reset_ubwc(struct sde_hw_mdp *mdp, struct sde_mdss_cfg *m)

{

	struct sde_hw_blk_reg_map c;

	u32 ubwc_version;



	if (!mdp || !m)

		return;



	if (!IS_UBWC_20_SUPPORTED(m->ubwc_version))

		return;



	/* force blk offset to zero to access beginning of register region */

	c = mdp->hw;

	c.blk_off = 0x0;

	ubwc_version = SDE_REG_READ(&c, UBWC_DEC_HW_VERSION);



	if (IS_UBWC_20_SUPPORTED(ubwc_version)) {

		SDE_REG_WRITE(&c, UBWC_STATIC, m->mdp[0].ubwc_static);

	} else if (IS_UBWC_30_SUPPORTED(ubwc_version)) {

		u32 reg = m->mdp[0].ubwc_static |

			(m->mdp[0].ubwc_swizzle & 0x1) |

			((m->mdp[0].highest_bank_bit & 0x3) << 4) |

			((m->macrotile_mode & 0x1) << 12);



		if (IS_UBWC_30_SUPPORTED(m->ubwc_version))

			reg |= BIT(10);



		SDE_REG_WRITE(&c, UBWC_STATIC, reg);

	} else {

		SDE_ERROR("Unsupported UBWC version 0x%08x\n", ubwc_version);

	}

}



static void sde_hw_intf_audio_select(struct sde_hw_mdp *mdp)