Loading arch/arm64/boot/dts/qcom/sm8150.dtsi +5 −0 Original line number Diff line number Diff line Loading @@ -687,6 +687,11 @@ label = "cont_splash_region"; }; disp_rdump_memory: disp_rdump_region@9c000000 { reg = <0x0 0x9c000000 0x0 0x00800000>; label = "disp_rdump_region"; }; adsp_mem: adsp_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; Loading drivers/gpu/drm/msm/sde/sde_hw_dspp.c +5 −3 Original line number Diff line number Diff line Loading @@ -45,7 +45,7 @@ static struct sde_dspp_cfg *_dspp_offset(enum sde_dspp dspp, static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features) { int i = 0, ret; int i = 0, ret = 0; if (!c || !c->cap || !c->cap->sblk) return; Loading @@ -71,7 +71,7 @@ static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features) break; case SDE_DSPP_HSIC: if (c->cap->sblk->hsic.version == SDE_COLOR_PROCESS_VER(0x1, 0x7)) SDE_COLOR_PROCESS_VER(0x1, 0x7)) { ret = reg_dmav1_init_dspp_op_v4(i, c->idx); if (!ret) c->ops.setup_pa_hsic = Loading @@ -79,6 +79,7 @@ static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features) else c->ops.setup_pa_hsic = sde_setup_dspp_pa_hsic_v17; } break; case SDE_DSPP_MEMCOLOR: if (c->cap->sblk->memcolor.version == Loading Loading @@ -107,7 +108,7 @@ static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features) break; case SDE_DSPP_SIXZONE: if (c->cap->sblk->sixzone.version == SDE_COLOR_PROCESS_VER(0x1, 0x7)) SDE_COLOR_PROCESS_VER(0x1, 0x7)) { ret = reg_dmav1_init_dspp_op_v4(i, c->idx); if (!ret) c->ops.setup_sixzone = Loading @@ -115,6 +116,7 @@ static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features) else c->ops.setup_sixzone = sde_setup_dspp_sixzone_v17; } break; case SDE_DSPP_DITHER: if (c->cap->sblk->dither.version == Loading drivers/gpu/drm/msm/sde/sde_hw_mdss.h +5 −0 Original line number Diff line number Diff line Loading @@ -579,6 +579,9 @@ struct ctl_top { * @splash_base: Base address of continuous splash region reserved * by bootloader * @splash_size: Size of continuous splash region * @ramdump_base: Base address of ramdump display region reserved * by bootloader * @ramdump_size: Size of ramdump buffer region * @top: struct ctl_top objects * @ctl_ids: stores the valid MDSS ctl block ids for the current mode * @lm_ids: stores the valid MDSS layer mixer block ids for the current mode Loading @@ -593,6 +596,8 @@ struct sde_splash_data { bool resource_handoff_pending; unsigned long splash_base; u32 splash_size; unsigned long ramdump_base; u32 ramdump_size; struct ctl_top top[CTL_MAX - CTL_0]; u8 ctl_ids[CTL_MAX - CTL_0]; u8 lm_ids[LM_MAX - LM_0]; Loading drivers/gpu/drm/msm/sde/sde_kms.c +37 −11 Original line number Diff line number Diff line Loading @@ -801,18 +801,22 @@ static int sde_kms_prepare_secure_transition(struct msm_kms *kms, } static int _sde_kms_release_splash_buffer(unsigned int mem_addr, unsigned int size) unsigned int splash_buffer_size, unsigned int ramdump_buffer_size) { unsigned long pfn_start, pfn_end, pfn_idx; int ret = 0; if (!mem_addr || !size) if (!mem_addr || !splash_buffer_size) SDE_ERROR("invalid params\n"); mem_addr += ramdump_buffer_size; splash_buffer_size -= ramdump_buffer_size; pfn_start = mem_addr >> PAGE_SHIFT; pfn_end = (mem_addr + size) >> PAGE_SHIFT; pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT; ret = memblock_free(mem_addr, size); ret = memblock_free(mem_addr, splash_buffer_size); if (ret) { SDE_ERROR("continuous splash memory free failed:%d\n", ret); return ret; Loading Loading @@ -993,7 +997,8 @@ static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms, rc = _sde_kms_release_splash_buffer( sde_kms->splash_data.splash_base, sde_kms->splash_data.splash_size); sde_kms->splash_data.splash_size, sde_kms->splash_data.ramdump_size); if (rc) pr_err("failed to release splash memory\n"); sde_kms->splash_data.splash_base = 0; Loading Loading @@ -1691,7 +1696,8 @@ static void _sde_kms_hw_destroy(struct sde_kms *sde_kms, _sde_kms_release_displays(sde_kms); (void)_sde_kms_release_splash_buffer( sde_kms->splash_data.splash_base, sde_kms->splash_data.splash_size); sde_kms->splash_data.splash_size, sde_kms->splash_data.ramdump_size); /* safe to call these more than once during shutdown */ _sde_debugfs_destroy(sde_kms); Loading Loading @@ -2803,8 +2809,8 @@ static int sde_kms_pd_disable(struct generic_pm_domain *genpd) static int _sde_kms_get_splash_data(struct sde_splash_data *data) { int ret = 0; struct device_node *parent, *node; struct resource r; struct device_node *parent, *node, *node1; struct resource r, r1; if (!data) return -EINVAL; Loading @@ -2829,9 +2835,29 @@ static int _sde_kms_get_splash_data(struct sde_splash_data *data) data->splash_base = (unsigned long)r.start; data->splash_size = (r.end - r.start) + 1; pr_info("found continuous splash base address:%lx size:%x\n", data->splash_base, data->splash_size); node1 = of_find_node_by_name(parent, "disp_rdump_region"); if (!node1) SDE_DEBUG("failed to find disp ramdump memory reservation\n"); if (!node1 || of_address_to_resource(node1, 0, &r1)) { SDE_DEBUG("failed to find data for disp ramdump memory\n"); data->ramdump_base = 0; data->ramdump_size = 0; } else { data->ramdump_base = (unsigned long)r1.start; data->ramdump_size = (r1.end - r1.start) + 1; } if ((data->ramdump_base && data->ramdump_base != data->splash_base) || (data->ramdump_size > data->splash_size)) { SDE_ERROR("ramdump/splash buffer addr/size mismatched\n"); data->ramdump_base = 0; data->ramdump_size = 0; } pr_info("cont spla base adds:%lx size:%x rdump adds=:%lx size:%x\n", data->splash_base, data->splash_size, data->ramdump_base, data->ramdump_size); return ret; } Loading Loading
arch/arm64/boot/dts/qcom/sm8150.dtsi +5 −0 Original line number Diff line number Diff line Loading @@ -687,6 +687,11 @@ label = "cont_splash_region"; }; disp_rdump_memory: disp_rdump_region@9c000000 { reg = <0x0 0x9c000000 0x0 0x00800000>; label = "disp_rdump_region"; }; adsp_mem: adsp_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; Loading
drivers/gpu/drm/msm/sde/sde_hw_dspp.c +5 −3 Original line number Diff line number Diff line Loading @@ -45,7 +45,7 @@ static struct sde_dspp_cfg *_dspp_offset(enum sde_dspp dspp, static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features) { int i = 0, ret; int i = 0, ret = 0; if (!c || !c->cap || !c->cap->sblk) return; Loading @@ -71,7 +71,7 @@ static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features) break; case SDE_DSPP_HSIC: if (c->cap->sblk->hsic.version == SDE_COLOR_PROCESS_VER(0x1, 0x7)) SDE_COLOR_PROCESS_VER(0x1, 0x7)) { ret = reg_dmav1_init_dspp_op_v4(i, c->idx); if (!ret) c->ops.setup_pa_hsic = Loading @@ -79,6 +79,7 @@ static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features) else c->ops.setup_pa_hsic = sde_setup_dspp_pa_hsic_v17; } break; case SDE_DSPP_MEMCOLOR: if (c->cap->sblk->memcolor.version == Loading Loading @@ -107,7 +108,7 @@ static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features) break; case SDE_DSPP_SIXZONE: if (c->cap->sblk->sixzone.version == SDE_COLOR_PROCESS_VER(0x1, 0x7)) SDE_COLOR_PROCESS_VER(0x1, 0x7)) { ret = reg_dmav1_init_dspp_op_v4(i, c->idx); if (!ret) c->ops.setup_sixzone = Loading @@ -115,6 +116,7 @@ static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features) else c->ops.setup_sixzone = sde_setup_dspp_sixzone_v17; } break; case SDE_DSPP_DITHER: if (c->cap->sblk->dither.version == Loading
drivers/gpu/drm/msm/sde/sde_hw_mdss.h +5 −0 Original line number Diff line number Diff line Loading @@ -579,6 +579,9 @@ struct ctl_top { * @splash_base: Base address of continuous splash region reserved * by bootloader * @splash_size: Size of continuous splash region * @ramdump_base: Base address of ramdump display region reserved * by bootloader * @ramdump_size: Size of ramdump buffer region * @top: struct ctl_top objects * @ctl_ids: stores the valid MDSS ctl block ids for the current mode * @lm_ids: stores the valid MDSS layer mixer block ids for the current mode Loading @@ -593,6 +596,8 @@ struct sde_splash_data { bool resource_handoff_pending; unsigned long splash_base; u32 splash_size; unsigned long ramdump_base; u32 ramdump_size; struct ctl_top top[CTL_MAX - CTL_0]; u8 ctl_ids[CTL_MAX - CTL_0]; u8 lm_ids[LM_MAX - LM_0]; Loading
drivers/gpu/drm/msm/sde/sde_kms.c +37 −11 Original line number Diff line number Diff line Loading @@ -801,18 +801,22 @@ static int sde_kms_prepare_secure_transition(struct msm_kms *kms, } static int _sde_kms_release_splash_buffer(unsigned int mem_addr, unsigned int size) unsigned int splash_buffer_size, unsigned int ramdump_buffer_size) { unsigned long pfn_start, pfn_end, pfn_idx; int ret = 0; if (!mem_addr || !size) if (!mem_addr || !splash_buffer_size) SDE_ERROR("invalid params\n"); mem_addr += ramdump_buffer_size; splash_buffer_size -= ramdump_buffer_size; pfn_start = mem_addr >> PAGE_SHIFT; pfn_end = (mem_addr + size) >> PAGE_SHIFT; pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT; ret = memblock_free(mem_addr, size); ret = memblock_free(mem_addr, splash_buffer_size); if (ret) { SDE_ERROR("continuous splash memory free failed:%d\n", ret); return ret; Loading Loading @@ -993,7 +997,8 @@ static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms, rc = _sde_kms_release_splash_buffer( sde_kms->splash_data.splash_base, sde_kms->splash_data.splash_size); sde_kms->splash_data.splash_size, sde_kms->splash_data.ramdump_size); if (rc) pr_err("failed to release splash memory\n"); sde_kms->splash_data.splash_base = 0; Loading Loading @@ -1691,7 +1696,8 @@ static void _sde_kms_hw_destroy(struct sde_kms *sde_kms, _sde_kms_release_displays(sde_kms); (void)_sde_kms_release_splash_buffer( sde_kms->splash_data.splash_base, sde_kms->splash_data.splash_size); sde_kms->splash_data.splash_size, sde_kms->splash_data.ramdump_size); /* safe to call these more than once during shutdown */ _sde_debugfs_destroy(sde_kms); Loading Loading @@ -2803,8 +2809,8 @@ static int sde_kms_pd_disable(struct generic_pm_domain *genpd) static int _sde_kms_get_splash_data(struct sde_splash_data *data) { int ret = 0; struct device_node *parent, *node; struct resource r; struct device_node *parent, *node, *node1; struct resource r, r1; if (!data) return -EINVAL; Loading @@ -2829,9 +2835,29 @@ static int _sde_kms_get_splash_data(struct sde_splash_data *data) data->splash_base = (unsigned long)r.start; data->splash_size = (r.end - r.start) + 1; pr_info("found continuous splash base address:%lx size:%x\n", data->splash_base, data->splash_size); node1 = of_find_node_by_name(parent, "disp_rdump_region"); if (!node1) SDE_DEBUG("failed to find disp ramdump memory reservation\n"); if (!node1 || of_address_to_resource(node1, 0, &r1)) { SDE_DEBUG("failed to find data for disp ramdump memory\n"); data->ramdump_base = 0; data->ramdump_size = 0; } else { data->ramdump_base = (unsigned long)r1.start; data->ramdump_size = (r1.end - r1.start) + 1; } if ((data->ramdump_base && data->ramdump_base != data->splash_base) || (data->ramdump_size > data->splash_size)) { SDE_ERROR("ramdump/splash buffer addr/size mismatched\n"); data->ramdump_base = 0; data->ramdump_size = 0; } pr_info("cont spla base adds:%lx size:%x rdump adds=:%lx size:%x\n", data->splash_base, data->splash_size, data->ramdump_base, data->ramdump_size); return ret; } Loading