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Commit fac956cb authored by Tony Truong's avatar Tony Truong
Browse files

ARM: dts: msm: realign PCIe1 SIDs to base SID for SM8150 



PCIe core generates SID based on BDF (bus, device, function)
hashing. Since root complex (RC) BDF is 0, the core will map it
to the first zero out register which is its base SID. Realign
all PCIe1 SIDs to its base SID for SM8150.

Change-Id: I718640e5397983d62a946d3849358e978ca06cb4
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent 76f60b6d

arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi

+16 −16
Original line number Diff line number Diff line
@@ -543,22 +543,22 @@ 


		qcom,smmu-sid-base = <0x1e00>;



		iommu-map = <0x0 &apps_smmu 0x1e10 0x1>,

			<0x100 &apps_smmu 0x1e11 0x1>,

			<0x200 &apps_smmu 0x1e12 0x1>,

			<0x300 &apps_smmu 0x1e13 0x1>,

			<0x400 &apps_smmu 0x1e14 0x1>,

			<0x500 &apps_smmu 0x1e15 0x1>,

			<0x600 &apps_smmu 0x1e16 0x1>,

			<0x700 &apps_smmu 0x1e17 0x1>,

			<0x800 &apps_smmu 0x1e18 0x1>,

			<0x900 &apps_smmu 0x1e19 0x1>,

			<0xa00 &apps_smmu 0x1e1a 0x1>,

			<0xb00 &apps_smmu 0x1e1b 0x1>,

			<0xc00 &apps_smmu 0x1e1c 0x1>,

			<0xd00 &apps_smmu 0x1e1d 0x1>,

			<0xe00 &apps_smmu 0x1e1e 0x1>,

			<0xf00 &apps_smmu 0x1e1f 0x1>;

		iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,

			<0x100 &apps_smmu 0x1e01 0x1>,

			<0x200 &apps_smmu 0x1e02 0x1>,

			<0x300 &apps_smmu 0x1e03 0x1>,

			<0x400 &apps_smmu 0x1e04 0x1>,

			<0x500 &apps_smmu 0x1e05 0x1>,

			<0x600 &apps_smmu 0x1e06 0x1>,

			<0x700 &apps_smmu 0x1e07 0x1>,

			<0x800 &apps_smmu 0x1e08 0x1>,

			<0x900 &apps_smmu 0x1e09 0x1>,

			<0xa00 &apps_smmu 0x1e0a 0x1>,

			<0xb00 &apps_smmu 0x1e0b 0x1>,

			<0xc00 &apps_smmu 0x1e0c 0x1>,

			<0xd00 &apps_smmu 0x1e0d 0x1>,

			<0xe00 &apps_smmu 0x1e0e 0x1>,

			<0xf00 &apps_smmu 0x1e0f 0x1>;



		qcom,msm-bus,name = "pcie1";

		qcom,msm-bus,num-cases = <2>;