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Commit fabc12f8 authored by Jilai Wang's avatar Jilai Wang
Browse files

msm: npu: Disable npu post clocks separately 



NPU post clocks are enabled after fw is loaded, so they should be
disabled before fw is unloaded. This change is to separate
npu_disable_core_clocks into npu_disable_core_clocks and
npu_disable_post_pil_clocks.

Change-Id: I81dd23ab4f40e3dc991b9c4404b9ebcef9259451
Signed-off-by: default avatarJilai Wang <jilaiw@codeaurora.org>
parent 853d7314

drivers/media/platform/msm/npu/npu_common.h

+1 −0
Original line number Diff line number Diff line
@@ -219,6 +219,7 @@ void npu_debugfs_deinit(struct npu_device *npu_dev); 
int npu_enable_core_power(struct npu_device *npu_dev);

void npu_disable_core_power(struct npu_device *npu_dev);

int npu_enable_post_pil_clocks(struct npu_device *npu_dev);

void npu_disable_post_pil_clocks(struct npu_device *npu_dev);



irqreturn_t npu_intr_hdler(int irq, void *ptr);

drivers/media/platform/msm/npu/npu_dev.c

+26 −7
Original line number Diff line number Diff line
@@ -50,7 +50,9 @@ 
 */

static int npu_enable_regulators(struct npu_device *npu_dev);

static void npu_disable_regulators(struct npu_device *npu_dev);

static int npu_enable_core_clocks(struct npu_device *npu_dev, bool post_pil);

static int npu_enable_clocks(struct npu_device *npu_dev, bool post_pil);

static void npu_disable_clocks(struct npu_device *npu_dev, bool post_pil);

static int npu_enable_core_clocks(struct npu_device *npu_dev);

static void npu_disable_core_clocks(struct npu_device *npu_dev);

static uint32_t npu_calc_power_level(struct npu_device *npu_dev);

static ssize_t npu_show_capabilities(struct device *dev,
@@ -280,7 +282,7 @@ int npu_enable_core_power(struct npu_device *npu_dev) 
		if (ret)

			return ret;



		ret = npu_enable_core_clocks(npu_dev, false);

		ret = npu_enable_core_clocks(npu_dev);

		if (ret) {

			npu_disable_regulators(npu_dev);

			pwr->pwr_vote_num = 0;
@@ -312,11 +314,25 @@ void npu_disable_core_power(struct npu_device *npu_dev) 
		pwr->default_pwrlevel);

}



static int npu_enable_core_clocks(struct npu_device *npu_dev)

{

	return npu_enable_clocks(npu_dev, false);

}



static void npu_disable_core_clocks(struct npu_device *npu_dev)

{

	return npu_disable_clocks(npu_dev, false);

}



int npu_enable_post_pil_clocks(struct npu_device *npu_dev)

{

	return npu_enable_core_clocks(npu_dev, true);

	return npu_enable_clocks(npu_dev, true);

}



void npu_disable_post_pil_clocks(struct npu_device *npu_dev)

{

	npu_disable_clocks(npu_dev, true);

}



static uint32_t npu_calc_power_level(struct npu_device *npu_dev)

{
@@ -499,7 +515,7 @@ static bool npu_is_exclude_rate_clock(const char *clk_name) 
	return ret;

}



static int npu_enable_core_clocks(struct npu_device *npu_dev, bool post_pil)

static int npu_enable_clocks(struct npu_device *npu_dev, bool post_pil)

{

	int i, rc = 0;

	struct npu_clk *core_clks = npu_dev->core_clks;
@@ -559,14 +575,17 @@ static int npu_enable_core_clocks(struct npu_device *npu_dev, bool post_pil) 
	return rc;

}



static void npu_disable_core_clocks(struct npu_device *npu_dev)

static void npu_disable_clocks(struct npu_device *npu_dev, bool post_pil)

{

	int i = 0;

	struct npu_clk *core_clks = npu_dev->core_clks;



	for (i = (npu_dev->core_clk_num)-1; i >= 0 ; i--) {

		if (npu_dev->host_ctx.fw_state == FW_DISABLED) {

			if (npu_is_post_clock(npu_dev->core_clks[i].clk_name))

		if (post_pil) {

			if (!npu_is_post_clock(core_clks[i].clk_name))

				continue;

		} else {

			if (npu_is_post_clock(core_clks[i].clk_name))

				continue;

		}

drivers/media/platform/msm/npu/npu_mgr.c

+9 −1
Original line number Diff line number Diff line
@@ -91,6 +91,11 @@ int fw_init(struct npu_device *npu_dev) 


	/* Boot the NPU subsystem */

	host_ctx->subsystem_handle = subsystem_get_local("npu");

	if (IS_ERR(host_ctx->subsystem_handle)) {

		pr_err("pil load npu fw failed\n");

		ret = -ENODEV;

		goto subsystem_get_fail;

	}



	/* Clear control/status registers */

	REGW(npu_dev, REG_NPU_FW_CTRL_STATUS, 0x0);
@@ -149,8 +154,10 @@ int fw_init(struct npu_device *npu_dev) 
	return ret;



wait_fw_ready_fail:

	subsystem_put_local(host_ctx->subsystem_handle);

	npu_disable_post_pil_clocks(npu_dev);

enable_post_clk_fail:

	subsystem_put_local(host_ctx->subsystem_handle);

subsystem_get_fail:

	npu_disable_sys_cache(npu_dev);

enable_sys_cache_fail:

	npu_disable_core_power(npu_dev);
@@ -194,6 +201,7 @@ void fw_deinit(struct npu_device *npu_dev, bool fw_alive) 
	}



	npu_disable_irq(npu_dev);

	npu_disable_post_pil_clocks(npu_dev);

	npu_disable_sys_cache(npu_dev);

	subsystem_put_local(host_ctx->subsystem_handle);

	host_ctx->fw_state = FW_DISABLED;