Merge branch 'clk-next-rockchip' into clk-next (fa531042) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/clk/rockchip/clk-rk3288.c

+56 −36

Original line number	Diff line number	Diff line
		@@ -143,7 +143,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
		[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
		RK3288_MODE_CON, 12, 8, rk3288_pll_rates),
		[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
		RK3288_MODE_CON, 14, 9, NULL),
		RK3288_MODE_CON, 14, 9, rk3288_pll_rates),
		};

		static struct clk_div_table div_hclk_cpu_t[] = {
		@@ -219,12 +219,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
		RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
		DIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0,
		RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
		GATE(0, "aclk_cpu", "aclk_cpu_pre", 0,
		GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,
		RK3288_CLKGATE_CON(0), 3, GFLAGS),
		COMPOSITE_NOMUX(0, "pclk_cpu", "aclk_cpu_pre", 0,
		COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", 0,
		RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
		RK3288_CLKGATE_CON(0), 5, GFLAGS),
		COMPOSITE_NOMUX_DIVTBL(0, "hclk_cpu", "aclk_cpu_pre", 0,
		COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", 0,
		RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
		RK3288_CLKGATE_CON(0), 4, GFLAGS),
		GATE(0, "c2c_host", "aclk_cpu_src", 0,
		@@ -296,6 +296,20 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
		COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
		RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
		RK3288_CLKGATE_CON(3), 11, GFLAGS),
		/*
		* We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system,
		* so we ignore the mux and make clocks nodes as following,
		*/
		GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0,
		RK3288_CLKGATE_CON(9), 0, GFLAGS),
		/*
		* We introduce a virtul node of hclk_vodec_pre_v to split one clock
		* struct with a gate and a fix divider into two node in software.
		*/
		GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0,
		RK3288_CLKGATE_CON(3), 10, GFLAGS),
		GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
		RK3288_CLKGATE_CON(9), 1, GFLAGS),

		COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0,
		RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
		@@ -309,7 +323,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
		COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0,
		RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS,
		RK3288_CLKGATE_CON(3), 5, GFLAGS),
		COMPOSITE(0, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
		COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
		RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
		RK3288_CLKGATE_CON(3), 4, GFLAGS),

		@@ -320,35 +334,35 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
		RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
		RK3288_CLKGATE_CON(3), 3, GFLAGS),

		COMPOSITE_NODIV(0, "sclk_edp_24m", mux_edp_24m_p, 0,
		COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
		RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
		RK3288_CLKGATE_CON(3), 12, GFLAGS),
		COMPOSITE(0, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
		COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
		RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
		RK3288_CLKGATE_CON(3), 13, GFLAGS),

		COMPOSITE(0, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
		COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
		RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
		RK3288_CLKGATE_CON(3), 14, GFLAGS),
		COMPOSITE(0, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
		COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
		RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
		RK3288_CLKGATE_CON(3), 15, GFLAGS),

		GATE(0, "sclk_hdmi_hdcp", "xin24m", 0,
		GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
		RK3288_CLKGATE_CON(5), 12, GFLAGS),
		GATE(0, "sclk_hdmi_cec", "xin32k", 0,
		GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
		RK3288_CLKGATE_CON(5), 11, GFLAGS),

		COMPOSITE(0, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
		COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
		RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
		RK3288_CLKGATE_CON(13), 13, GFLAGS),
		DIV(0, "hclk_hevc", "aclk_hevc", 0,
		DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
		RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),

		COMPOSITE(0, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
		COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
		RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
		RK3288_CLKGATE_CON(13), 14, GFLAGS),
		COMPOSITE(0, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
		COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
		RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
		RK3288_CLKGATE_CON(13), 15, GFLAGS),

		@@ -371,13 +385,13 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
		COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, 0,
		RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
		RK3288_CLKGATE_CON(2), 0, GFLAGS),
		COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_src", 0,
		COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
		RK3288_CLKSEL_CON(10), 12, 2, DFLAGS \| CLK_DIVIDER_POWER_OF_TWO,
		RK3288_CLKGATE_CON(2), 3, GFLAGS),
		COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_src", 0,
		COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
		RK3288_CLKSEL_CON(10), 8, 2, DFLAGS \| CLK_DIVIDER_POWER_OF_TWO,
		RK3288_CLKGATE_CON(2), 2, GFLAGS),
		GATE(0, "aclk_peri", "aclk_peri_src", 0,
		GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
		RK3288_CLKGATE_CON(2), 1, GFLAGS),

		/*
		@@ -643,34 +657,34 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
		GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
		GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
		GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
		GATE(0, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS),
		GATE(0, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS),
		GATE(0, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
		GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS),
		GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS),
		GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
		GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
		GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
		GATE(0, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS),
		GATE(0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
		GATE(0, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
		GATE(0, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
		GATE(0, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
		GATE(0, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS),
		GATE(0, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
		GATE(0, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS),
		GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS),
		GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
		GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
		GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
		GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
		GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS),
		GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
		GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS),

		/* aclk_vio0 gates */
		GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
		GATE(0, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
		GATE(0, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS),
		GATE(0, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
		GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
		GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS),
		GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),

		/* aclk_vio1 gates */
		GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
		GATE(0, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
		GATE(0, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),
		GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
		GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),

		/* aclk_rga_pre gates */
		GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
		GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),
		GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),

		/*
		* Other ungrouped clocks.
		@@ -711,6 +725,12 @@ static void __init rk3288_clk_init(struct device_node *np)
		pr_warn("%s: could not register clock usb480m: %ld\n",
		__func__, PTR_ERR(clk));

		clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre",
		"hclk_vcodec_pre_v", 0, 1, 4);
		if (IS_ERR(clk))
		pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
		__func__, PTR_ERR(clk));

		rockchip_clk_register_plls(rk3288_pll_clks,
		ARRAY_SIZE(rk3288_pll_clks),
		RK3288_GRF_SOC_STATUS);
		@@ -719,7 +739,7 @@ static void __init rk3288_clk_init(struct device_node *np)
		rockchip_clk_protect_critical(rk3288_critical_clocks,
		ARRAY_SIZE(rk3288_critical_clocks));

		rockchip_register_softrst(np, 9, reg_base + RK3288_SOFTRST_CON(0),
		rockchip_register_softrst(np, 12, reg_base + RK3288_SOFTRST_CON(0),
		ROCKCHIP_SOFTRST_HIWORD_MASK);
		}
		CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);

include/dt-bindings/clock/rk3288-cru.h

+80 −1

Original line number	Diff line number	Diff line
		@@ -61,6 +61,15 @@
		#define SCLK_LCDC_PWM1 101
		#define SCLK_MAC_RX 102
		#define SCLK_MAC_TX 103
		#define SCLK_EDP_24M 104
		#define SCLK_EDP 105
		#define SCLK_RGA 106
		#define SCLK_ISP 107
		#define SCLK_ISP_JPE 108
		#define SCLK_HDMI_HDCP 109
		#define SCLK_HDMI_CEC 110
		#define SCLK_HEVC_CABAC 111
		#define SCLK_HEVC_CORE 112

		#define DCLK_VOP0 190
		#define DCLK_VOP1 191
		@@ -75,6 +84,16 @@
		#define ACLK_VOP1 198
		#define ACLK_CRYPTO 199
		#define ACLK_RGA 200
		#define ACLK_RGA_NIU 201
		#define ACLK_IEP 202
		#define ACLK_VIO0_NIU 203
		#define ACLK_VIP 204
		#define ACLK_ISP 205
		#define ACLK_VIO1_NIU 206
		#define ACLK_HEVC 207
		#define ACLK_VCODEC 208
		#define ACLK_CPU 209
		#define ACLK_PERI 210

		/* pclk gates */
		#define PCLK_GPIO0 320
		@@ -112,6 +131,15 @@
		#define PCLK_PS2C 352
		#define PCLK_TIMER 353
		#define PCLK_TZPC 354
		#define PCLK_EDP_CTRL 355
		#define PCLK_MIPI_DSI0 356
		#define PCLK_MIPI_DSI1 357
		#define PCLK_MIPI_CSI 358
		#define PCLK_LVDS_PHY 359
		#define PCLK_HDMI_CTRL 360
		#define PCLK_VIO2_H2P 361
		#define PCLK_CPU 362
		#define PCLK_PERI 363

		/* hclk gates */
		#define HCLK_GPS 448
		@@ -137,8 +165,16 @@
		#define HCLK_IEP 468
		#define HCLK_ISP 469
		#define HCLK_RGA 470
		#define HCLK_VIO_AHB_ARBI 471
		#define HCLK_VIO_NIU 472
		#define HCLK_VIP 473
		#define HCLK_VIO2_H2P 474
		#define HCLK_HEVC 475
		#define HCLK_VCODEC 476
		#define HCLK_CPU 477
		#define HCLK_PERI 478

		#define CLK_NR_CLKS (HCLK_RGA + 1)
		#define CLK_NR_CLKS (HCLK_PERI + 1)

		/* soft-reset indices */
		#define SRST_CORE0 0
		@@ -276,3 +312,46 @@
		#define SRST_USBHOST1_CON 140
		#define SRST_USB_ADP 141
		#define SRST_ACC_EFUSE 142

		#define SRST_CORESIGHT 144
		#define SRST_PD_CORE_AHB_NOC 145
		#define SRST_PD_CORE_APB_NOC 146
		#define SRST_PD_CORE_MP_AXI 147
		#define SRST_GIC 148
		#define SRST_LCDC_PWM0 149
		#define SRST_LCDC_PWM1 150
		#define SRST_VIO0_H2P_BRG 151
		#define SRST_VIO1_H2P_BRG 152
		#define SRST_RGA_H2P_BRG 153
		#define SRST_HEVC 154
		#define SRST_TSADC 159

		#define SRST_DDRPHY0 160
		#define SRST_DDRPHY0_APB 161
		#define SRST_DDRCTRL0 162
		#define SRST_DDRCTRL0_APB 163
		#define SRST_DDRPHY0_CTRL 164
		#define SRST_DDRPHY1 165
		#define SRST_DDRPHY1_APB 166
		#define SRST_DDRCTRL1 167
		#define SRST_DDRCTRL1_APB 168
		#define SRST_DDRPHY1_CTRL 169
		#define SRST_DDRMSCH0 170
		#define SRST_DDRMSCH1 171
		#define SRST_CRYPTO 174
		#define SRST_C2C_HOST 175

		#define SRST_LCDC1_AXI 176
		#define SRST_LCDC1_AHB 177
		#define SRST_LCDC1_DCLK 178
		#define SRST_UART0 179
		#define SRST_UART1 180
		#define SRST_UART2 181
		#define SRST_UART3 182
		#define SRST_UART4 183
		#define SRST_SIMC 186
		#define SRST_PS2C 187
		#define SRST_TSP 188
		#define SRST_TSP_CLKIN0 189
		#define SRST_TSP_CLKIN1 190
		#define SRST_TSP_27M 191