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Commit fa1571bc authored by Mao Jinlong's avatar Mao Jinlong Committed by Tingwei Zhang
Browse files

ARM: dts: msm: Add tpdm gpu for TRINKET



Add tpdm gpu for TRINKET to support sinks in getting gpu hardware
events.

Change-Id: Iea3c911673621a82483d90dbc3d2c1e6d3118363
Signed-off-by: default avatarMao Jinlong <jinlmao@codeaurora.org>
Signed-off-by: default avatarTingwei Zhang <tingwei@codeaurora.org>
parent 88f8f14a
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+86 −9
Original line number Diff line number Diff line
@@ -232,7 +232,7 @@
		reg = <0x8042000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-in2";
		coresight-name = "coresight-funnel-in1";

		clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
@@ -924,6 +924,15 @@
			};

			port@2 {
				reg = <1>;
				tpda_in_funnel_gpu: endpoint {
					slave-mode;
					remote-endpoint =
						<&funnel_gpu_out_tpda>;
				};
			};

			port@3 {
				reg = <3>;
				tpda_in_funnel_monaq: endpoint {
					slave-mode;
@@ -932,7 +941,7 @@
				};
			};

			port@3 {
			port@4 {
				reg = <4>;
				tpda_in_funnel_lpass_1: endpoint {
					slave-mode;
@@ -941,7 +950,7 @@
				};
			};

			port@4 {
			port@5 {
				reg = <5>;
				tpda_in_funnel_turing: endpoint {
					slave-mode;
@@ -950,7 +959,7 @@
				};
			};

			port@5 {
			port@6 {
				reg = <7>;
				tpda_in_tpdm_vsense: endpoint {
					slave-mode;
@@ -959,7 +968,7 @@
				};
			};

			port@6 {
			port@7 {
				reg = <8>;
				tpda_in_tpdm_dcc: endpoint {
					slave-mode;
@@ -968,7 +977,7 @@
				};
			};

			port@7 {
			port@8 {
				reg = <10>;
				tpda_in_tpdm_prng: endpoint {
					slave-mode;
@@ -977,7 +986,7 @@
				};
			};

			port@8 {
			port@9 {
				reg = <12>;
				tpda_in_tpdm_qm: endpoint {
					slave-mode;
@@ -986,7 +995,7 @@
				};
			};

			port@9 {
			port@10 {
				reg = <13>;
				tpda_in_tpdm_west: endpoint {
					slave-mode;
@@ -995,7 +1004,7 @@
				};
			};

			port@10 {
			port@11 {
				reg = <14>;
				tpda_in_tpdm_pimem: endpoint {
					slave-mode;
@@ -1007,6 +1016,74 @@
		};
	};

	funnel_gpu: funnel@8944000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x8944000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-gpu";

		clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
			<&clock_gpucc GPU_CC_CX_APB_CLK>;
		clock-names = "apb_pclk", "gpu_apb_clk";
		qcom,proxy-clks = "gpu_apb_clk";

		vddcx-supply = <&gpu_cx_gdsc>;
		vdd-supply = <&gpu_gx_gdsc>;
		regulator-names = "vddcx", "vdd";
		qcom,proxy-regs  = "vddcx", "vdd";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_gpu_out_tpda: endpoint {
					remote-endpoint =
					  <&tpda_in_funnel_gpu>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_gpu_in_tpdm_gpu: endpoint {
					slave-mode;
					remote-endpoint =
					  <&tpdm_gpu_out_funnel_gpu>;
				};
			};
		};
	};

	tpdm_gpu: tpdm@8940000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x8940000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-gpu";

		clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
			<&clock_gpucc GPU_CC_CX_APB_CLK>;
		clock-names = "apb_pclk", "gpu_apb_clk";

		qcom,tpdm-clks = "gpu_apb_clk";

		vddcx-supply = <&gpu_cx_gdsc>;
		vdd-supply = <&gpu_gx_gdsc>;
		regulator-names = "vddcx", "vdd";
		qcom,tpdm-regs  = "vddcx", "vdd";

		port {
			tpdm_gpu_out_funnel_gpu: endpoint {
				remote-endpoint = <&funnel_gpu_in_tpdm_gpu>;
			};
		};
	};

	tpdm_vsense: tpdm@8840000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;