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Commit f9a1ef72 authored by Eugenia Emantayev's avatar Eugenia Emantayev Committed by Saeed Mahameed
Browse files

net/mlx5: Add MTPPS and MTPPSE registers infrastructure 



Implement query and set functionality for MTPPS and MTPPSE registers.
MTPPS (Management Pulse Per Second) provides the device PPS capabilities,
configures the PPS in and out modules and holds the PPS in time stamp.
Query MTPPS is supported only when HCA_CAP.pps is set and modify is supported
when HCA_CAP.pps_modify is set.

MTPPSE (Management Pulse Per Second Event) configures the different event
generation modes for PPS. Supported when HCA_CAP.pps is set.

Signed-off-by: default avatarEugenia Emantayev <eugenia@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
parent 712bfef6

drivers/net/ethernet/mellanox/mlx5/core/eq.c

+9 −0
Original line number Diff line number Diff line
@@ -154,6 +154,8 @@ static const char *eqe_type_str(u8 type) 
		return "MLX5_EVENT_TYPE_PAGE_REQUEST";

	case MLX5_EVENT_TYPE_PAGE_FAULT:

		return "MLX5_EVENT_TYPE_PAGE_FAULT";

	case MLX5_EVENT_TYPE_PPS_EVENT:

		return "MLX5_EVENT_TYPE_PPS_EVENT";

	default:

		return "Unrecognized event";

	}
@@ -470,6 +472,10 @@ static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr) 
			mlx5_port_module_event(dev, eqe);

			break;



		case MLX5_EVENT_TYPE_PPS_EVENT:

			if (dev->event)

				dev->event(dev, MLX5_DEV_EVENT_PPS, (unsigned long)eqe);

			break;

		default:

			mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",

				       eqe->type, eq->eqn);
@@ -684,6 +690,9 @@ int mlx5_start_eqs(struct mlx5_core_dev *dev) 
	else

		mlx5_core_dbg(dev, "port_module_event is not set\n");



	if (MLX5_CAP_GEN(dev, pps))

		async_event_mask |= (1ull << MLX5_EVENT_TYPE_PPS_EVENT);



	err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,

				 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,

				 "mlx5_cmd_eq", MLX5_EQ_TYPE_ASYNC);

drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h

+5 −0
Original line number Diff line number Diff line
@@ -138,6 +138,11 @@ void mlx5_encap_dealloc(struct mlx5_core_dev *dev, u32 encap_id); 


bool mlx5_lag_intf_add(struct mlx5_interface *intf, struct mlx5_priv *priv);



int mlx5_query_mtpps(struct mlx5_core_dev *dev, u32 *mtpps, u32 mtpps_size);

int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size);

int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode);

int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode);



void mlx5e_init(void);

void mlx5e_cleanup(void);

drivers/net/ethernet/mellanox/mlx5/core/port.c

+48 −0
Original line number Diff line number Diff line
@@ -866,3 +866,51 @@ void mlx5_port_module_event(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe) 
			       module_num, mlx5_pme_status[module_status - 1],

			       mlx5_pme_error[error_type]);

}



int mlx5_query_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)

{

	u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};



	return mlx5_core_access_reg(mdev, in, sizeof(in), mtpps,

				    mtpps_size, MLX5_REG_MTPPS, 0, 0);

}



int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)

{

	u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {0};



	return mlx5_core_access_reg(mdev, mtpps, mtpps_size, out,

				    sizeof(out), MLX5_REG_MTPPS, 0, 1);

}



int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode)

{

	u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};

	u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};

	int err = 0;



	MLX5_SET(mtppse_reg, in, pin, pin);



	err = mlx5_core_access_reg(mdev, in, sizeof(in), out,

				   sizeof(out), MLX5_REG_MTPPSE, 0, 0);

	if (err)

		return err;



	*arm = MLX5_GET(mtppse_reg, in, event_arm);

	*mode = MLX5_GET(mtppse_reg, in, event_generation_mode);



	return err;

}



int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode)

{

	u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};

	u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};



	MLX5_SET(mtppse_reg, in, pin, pin);

	MLX5_SET(mtppse_reg, in, event_arm, arm);

	MLX5_SET(mtppse_reg, in, event_generation_mode, mode);



	return mlx5_core_access_reg(mdev, in, sizeof(in), out,

				    sizeof(out), MLX5_REG_MTPPSE, 0, 1);

}

include/linux/mlx5/device.h

+18 −0
Original line number Diff line number Diff line
@@ -289,6 +289,7 @@ enum mlx5_event { 
	MLX5_EVENT_TYPE_GPIO_EVENT	   = 0x15,

	MLX5_EVENT_TYPE_PORT_MODULE_EVENT  = 0x16,

	MLX5_EVENT_TYPE_REMOTE_CONFIG	   = 0x19,

	MLX5_EVENT_TYPE_PPS_EVENT          = 0x25,



	MLX5_EVENT_TYPE_DB_BF_CONGESTION   = 0x1a,

	MLX5_EVENT_TYPE_STALL_EVENT	   = 0x1b,
@@ -569,6 +570,22 @@ struct mlx5_eqe_port_module { 
	u8        error_type;

} __packed;



struct mlx5_eqe_pps {

	u8		rsvd0[3];

	u8		pin;

	u8		rsvd1[4];

	union {

		struct {

			__be32		time_sec;

			__be32		time_nsec;

		};

		struct {

			__be64		time_stamp;

		};

	};

	u8		rsvd2[12];

} __packed;



union ev_data {

	__be32				raw[7];

	struct mlx5_eqe_cmd		cmd;
@@ -583,6 +600,7 @@ union ev_data { 
	struct mlx5_eqe_page_fault	page_fault;

	struct mlx5_eqe_vport_change	vport_change;

	struct mlx5_eqe_port_module	port_module;

	struct mlx5_eqe_pps		pps;

} __packed;



struct mlx5_eqe {

include/linux/mlx5/driver.h

+3 −0
Original line number Diff line number Diff line
@@ -125,6 +125,8 @@ enum { 
	MLX5_REG_HOST_ENDIANNESS = 0x7004,

	MLX5_REG_MCIA		 = 0x9014,

	MLX5_REG_MLCR		 = 0x902b,

	MLX5_REG_MTPPS		 = 0x9053,

	MLX5_REG_MTPPSE		 = 0x9054,

};



enum mlx5_dcbx_oper_mode {
@@ -172,6 +174,7 @@ enum mlx5_dev_event { 
	MLX5_DEV_EVENT_PKEY_CHANGE,

	MLX5_DEV_EVENT_GUID_CHANGE,

	MLX5_DEV_EVENT_CLIENT_REREG,

	MLX5_DEV_EVENT_PPS,

};



enum mlx5_port_status {