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Commit f999e175 authored by Jiten Patel's avatar Jiten Patel Committed by Ramandeep Trehan
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ARM: dts: msm: Add ice node for qcs405 



Add Inline Crypto Engine device node to support hardware encryption.

Change-Id: Ia7f58f34b22aa86babee47cdc67939d6b259f3c5
Signed-off-by: default avatarJiten Patel <jitepate@codeaurora.org>
parent f63747b8

arch/arm64/boot/dts/qcom/qcs405.dtsi

+23 −0
Original line number Diff line number Diff line
@@ -1083,6 +1083,28 @@ 
		clock-names = "iface_clk";

	};



	sdcc1_ice: sdcc1ice@7808000 {

		compatible = "qcom,ice";

		reg = <0x7808000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ice_core_clk_src", "ice_core_clk",

				"bus_clk", "iface_clk";

		clocks = <&clock_gcc SDCC1_ICE_CORE_CLK_SRC>,

			 <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,

			 <&clock_gcc GCC_SDCC1_AHB_CLK>,

			 <&clock_gcc GCC_SDCC1_APPS_CLK>;

		qcom,op-freq-hz = <266666667>, <0>, <0>, <0>;

		qcom,msm-bus,name = "sdcc_ice_noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<1 757 0 0>,    /* No vote */

				<1 757 1000 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "sdcc";

	};



	sdhc_1: sdhci@7804000 {

		compatible = "qcom,sdhci-msm-v5";

		reg = <0x7804000 0x1000>, <0x7805000 0x1000>;
@@ -1090,6 +1112,7 @@ 


		interrupts = <0 123 0>, <0 138 0>;

		interrupt-names = "hc_irq", "pwr_irq";

		sdhc-msm-crypto = <&sdcc1_ice>;



		qcom,bus-width = <8>;

		qcom,large-address-bus;