igb: Add Support for new i210/i211 devices. (f96a8a0b) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/net/ethernet/intel/igb/Makefile

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -33,6 +33,7 @@
	obj-$(CONFIG_IGB) += igb.o		obj-$(CONFIG_IGB) += igb.o

	igb-objs := igb_main.o igb_ethtool.o e1000_82575.o \		igb-objs := igb_main.o igb_ethtool.o e1000_82575.o \
	e1000_mac.o e1000_nvm.o e1000_phy.o e1000_mbx.o		e1000_mac.o e1000_nvm.o e1000_phy.o e1000_mbx.o \
			e1000_i210.o

	igb-$(CONFIG_IGB_PTP) += igb_ptp.o		igb-$(CONFIG_IGB_PTP) += igb_ptp.o

drivers/net/ethernet/intel/igb/e1000_82575.c

+136 −46

Original line number	Original line	Diff line number	Diff line
	@@ -36,6 +36,7 @@

	#include "e1000_mac.h"		#include "e1000_mac.h"
	#include "e1000_82575.h"		#include "e1000_82575.h"
			#include "e1000_i210.h"

	static s32 igb_get_invariants_82575(struct e1000_hw *);		static s32 igb_get_invariants_82575(struct e1000_hw *);
	static s32 igb_acquire_phy_82575(struct e1000_hw *);		static s32 igb_acquire_phy_82575(struct e1000_hw *);
	@@ -98,6 +99,8 @@ static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
	break;		break;
	case e1000_82580:		case e1000_82580:
	case e1000_i350:		case e1000_i350:
			case e1000_i210:
			case e1000_i211:
	reg = rd32(E1000_MDICNFG);		reg = rd32(E1000_MDICNFG);
	ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);		ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
	break;		break;
	@@ -152,6 +155,17 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
	case E1000_DEV_ID_I350_SGMII:		case E1000_DEV_ID_I350_SGMII:
	mac->type = e1000_i350;		mac->type = e1000_i350;
	break;		break;
			case E1000_DEV_ID_I210_COPPER:
			case E1000_DEV_ID_I210_COPPER_OEM1:
			case E1000_DEV_ID_I210_COPPER_IT:
			case E1000_DEV_ID_I210_FIBER:
			case E1000_DEV_ID_I210_SERDES:
			case E1000_DEV_ID_I210_SGMII:
			mac->type = e1000_i210;
			break;
			case E1000_DEV_ID_I211_COPPER:
			mac->type = e1000_i211;
			break;
	default:		default:
	return -E1000_ERR_MAC_INIT;		return -E1000_ERR_MAC_INIT;
	break;		break;
	@@ -184,26 +198,44 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
	/* Set mta register count */		/* Set mta register count */
	mac->mta_reg_count = 128;		mac->mta_reg_count = 128;
	/* Set rar entry count */		/* Set rar entry count */
	mac->rar_entry_count = E1000_RAR_ENTRIES_82575;		switch (mac->type) {
	if (mac->type == e1000_82576)		case e1000_82576:
	mac->rar_entry_count = E1000_RAR_ENTRIES_82576;		mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
	if (mac->type == e1000_82580)		break;
			case e1000_82580:
	mac->rar_entry_count = E1000_RAR_ENTRIES_82580;		mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
	if (mac->type == e1000_i350)		break;
			case e1000_i350:
			case e1000_i210:
			case e1000_i211:
	mac->rar_entry_count = E1000_RAR_ENTRIES_I350;		mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
			break;
			default:
			mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
			break;
			}
	/* reset */		/* reset */
	if (mac->type >= e1000_82580)		if (mac->type >= e1000_82580)
	mac->ops.reset_hw = igb_reset_hw_82580;		mac->ops.reset_hw = igb_reset_hw_82580;
	else		else
	mac->ops.reset_hw = igb_reset_hw_82575;		mac->ops.reset_hw = igb_reset_hw_82575;

			if (mac->type >= e1000_i210) {
			mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
			mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
			} else {
			mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
			mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
			}

	/* Set if part includes ASF firmware */		/* Set if part includes ASF firmware */
	mac->asf_firmware_present = true;		mac->asf_firmware_present = true;
	/* Set if manageability features are enabled. */		/* Set if manageability features are enabled. */
	mac->arc_subsystem_valid =		mac->arc_subsystem_valid =
	(rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)		(rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
	? true : false;		? true : false;
	/* enable EEE on i350 parts */		/* enable EEE on i350 parts and later parts */
	if (mac->type == e1000_i350)		if (mac->type >= e1000_i350)
	dev_spec->eee_disable = false;		dev_spec->eee_disable = false;
	else		else
	dev_spec->eee_disable = true;		dev_spec->eee_disable = true;
	@@ -215,7 +247,17 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)

	/* NVM initialization */		/* NVM initialization */
	eecd = rd32(E1000_EECD);		eecd = rd32(E1000_EECD);
			size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
			E1000_EECD_SIZE_EX_SHIFT);

			/*
			* Added to a constant, "size" becomes the left-shift value
			* for setting word_size.
			*/
			size += NVM_WORD_SIZE_BASE_SHIFT;

			nvm->word_size = 1 << size;
			if (hw->mac.type < e1000_i210) {
	nvm->opcode_bits = 8;		nvm->opcode_bits = 8;
	nvm->delay_usec = 1;		nvm->delay_usec = 1;
	switch (nvm->override) {		switch (nvm->override) {
	@@ -228,21 +270,18 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
	nvm->address_bits = 8;		nvm->address_bits = 8;
	break;		break;
	default:		default:
	nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;		nvm->page_size = eecd
	nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;		& E1000_EECD_ADDR_BITS ? 32 : 8;
			nvm->address_bits = eecd
			& E1000_EECD_ADDR_BITS ? 16 : 8;
	break;		break;
	}		}
			if (nvm->word_size == (1 << 15))
			nvm->page_size = 128;

	nvm->type = e1000_nvm_eeprom_spi;		nvm->type = e1000_nvm_eeprom_spi;
			} else
	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>		nvm->type = e1000_nvm_flash_hw;
	E1000_EECD_SIZE_EX_SHIFT);

	/*
	* Added to a constant, "size" becomes the left-shift value
	* for setting word_size.
	*/
	size += NVM_WORD_SIZE_BASE_SHIFT;

	/*		/*
	* Check for invalid size		* Check for invalid size
	@@ -251,32 +290,60 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
	pr_notice("The NVM size is not valid, defaulting to 32K\n");		pr_notice("The NVM size is not valid, defaulting to 32K\n");
	size = 15;		size = 15;
	}		}
	nvm->word_size = 1 << size;
	if (nvm->word_size == (1 << 15))
	nvm->page_size = 128;

	/* NVM Function Pointers */		/* NVM Function Pointers */
			switch (hw->mac.type) {
			case e1000_82580:
			nvm->ops.validate = igb_validate_nvm_checksum_82580;
			nvm->ops.update = igb_update_nvm_checksum_82580;
	nvm->ops.acquire = igb_acquire_nvm_82575;		nvm->ops.acquire = igb_acquire_nvm_82575;
			nvm->ops.release = igb_release_nvm_82575;
	if (nvm->word_size < (1 << 15))		if (nvm->word_size < (1 << 15))
	nvm->ops.read = igb_read_nvm_eerd;		nvm->ops.read = igb_read_nvm_eerd;
	else		else
	nvm->ops.read = igb_read_nvm_spi;		nvm->ops.read = igb_read_nvm_spi;
			nvm->ops.write = igb_write_nvm_spi;
	nvm->ops.release = igb_release_nvm_82575;
	switch (hw->mac.type) {
	case e1000_82580:
	nvm->ops.validate = igb_validate_nvm_checksum_82580;
	nvm->ops.update = igb_update_nvm_checksum_82580;
	break;		break;
	case e1000_i350:		case e1000_i350:
	nvm->ops.validate = igb_validate_nvm_checksum_i350;		nvm->ops.validate = igb_validate_nvm_checksum_i350;
	nvm->ops.update = igb_update_nvm_checksum_i350;		nvm->ops.update = igb_update_nvm_checksum_i350;
			nvm->ops.acquire = igb_acquire_nvm_82575;
			nvm->ops.release = igb_release_nvm_82575;
			if (nvm->word_size < (1 << 15))
			nvm->ops.read = igb_read_nvm_eerd;
			else
			nvm->ops.read = igb_read_nvm_spi;
			nvm->ops.write = igb_write_nvm_spi;
			break;
			case e1000_i210:
			nvm->ops.validate = igb_validate_nvm_checksum_i210;
			nvm->ops.update = igb_update_nvm_checksum_i210;
			nvm->ops.acquire = igb_acquire_nvm_i210;
			nvm->ops.release = igb_release_nvm_i210;
			nvm->ops.read = igb_read_nvm_srrd_i210;
			nvm->ops.valid_led_default = igb_valid_led_default_i210;
			break;
			case e1000_i211:
			nvm->ops.acquire = igb_acquire_nvm_i210;
			nvm->ops.release = igb_release_nvm_i210;
			nvm->ops.read = igb_read_nvm_i211;
			nvm->ops.valid_led_default = igb_valid_led_default_i210;
			nvm->ops.validate = NULL;
			nvm->ops.update = NULL;
			nvm->ops.write = NULL;
	break;		break;
	default:		default:
	nvm->ops.validate = igb_validate_nvm_checksum;		nvm->ops.validate = igb_validate_nvm_checksum;
	nvm->ops.update = igb_update_nvm_checksum;		nvm->ops.update = igb_update_nvm_checksum;
	}		nvm->ops.acquire = igb_acquire_nvm_82575;
			nvm->ops.release = igb_release_nvm_82575;
			if (nvm->word_size < (1 << 15))
			nvm->ops.read = igb_read_nvm_eerd;
			else
			nvm->ops.read = igb_read_nvm_spi;
	nvm->ops.write = igb_write_nvm_spi;		nvm->ops.write = igb_write_nvm_spi;
			break;
			}

	/* if part supports SR-IOV then initialize mailbox parameters */		/* if part supports SR-IOV then initialize mailbox parameters */
	switch (mac->type) {		switch (mac->type) {
	@@ -314,9 +381,13 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
	if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {		if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
	phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;		phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
	phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;		phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
	} else if (hw->mac.type >= e1000_82580) {		} else if ((hw->mac.type == e1000_82580)
			\|\| (hw->mac.type == e1000_i350)) {
	phy->ops.read_reg = igb_read_phy_reg_82580;		phy->ops.read_reg = igb_read_phy_reg_82580;
	phy->ops.write_reg = igb_write_phy_reg_82580;		phy->ops.write_reg = igb_write_phy_reg_82580;
			} else if (hw->phy.type >= e1000_phy_i210) {
			phy->ops.read_reg = igb_read_phy_reg_gs40g;
			phy->ops.write_reg = igb_write_phy_reg_gs40g;
	} else {		} else {
	phy->ops.read_reg = igb_read_phy_reg_igp;		phy->ops.read_reg = igb_read_phy_reg_igp;
	phy->ops.write_reg = igb_write_phy_reg_igp;		phy->ops.write_reg = igb_write_phy_reg_igp;
	@@ -345,6 +416,14 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
	else		else
	phy->ops.get_cable_length = igb_get_cable_length_m88;		phy->ops.get_cable_length = igb_get_cable_length_m88;

			if (phy->id == I210_I_PHY_ID) {
			phy->ops.get_cable_length =
			igb_get_cable_length_m88_gen2;
			phy->ops.set_d0_lplu_state =
			igb_set_d0_lplu_state_82580;
			phy->ops.set_d3_lplu_state =
			igb_set_d3_lplu_state_82580;
			}
	phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;		phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
	break;		break;
	case IGP03E1000_E_PHY_ID:		case IGP03E1000_E_PHY_ID:
	@@ -364,6 +443,15 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
	phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;		phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
	phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;		phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
	break;		break;
			case I210_I_PHY_ID:
			phy->type = e1000_phy_i210;
			phy->ops.get_phy_info = igb_get_phy_info_m88;
			phy->ops.check_polarity = igb_check_polarity_m88;
			phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
			phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
			phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
			phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
			break;
	default:		default:
	return -E1000_ERR_PHY;		return -E1000_ERR_PHY;
	}		}
	@@ -389,7 +477,7 @@ static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
	else if (hw->bus.func == E1000_FUNC_3)		else if (hw->bus.func == E1000_FUNC_3)
	mask = E1000_SWFW_PHY3_SM;		mask = E1000_SWFW_PHY3_SM;

	return igb_acquire_swfw_sync_82575(hw, mask);		return hw->mac.ops.acquire_swfw_sync(hw, mask);
	}		}

	/**		/**
	@@ -410,7 +498,7 @@ static void igb_release_phy_82575(struct e1000_hw *hw)
	else if (hw->bus.func == E1000_FUNC_3)		else if (hw->bus.func == E1000_FUNC_3)
	mask = E1000_SWFW_PHY3_SM;		mask = E1000_SWFW_PHY3_SM;

	igb_release_swfw_sync_82575(hw, mask);		hw->mac.ops.release_swfw_sync(hw, mask);
	}		}

	/**		/**
	@@ -514,6 +602,8 @@ static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
	break;		break;
	case e1000_82580:		case e1000_82580:
	case e1000_i350:		case e1000_i350:
			case e1000_i210:
			case e1000_i211:
	mdic = rd32(E1000_MDICNFG);		mdic = rd32(E1000_MDICNFG);
	mdic &= E1000_MDICNFG_PHY_MASK;		mdic &= E1000_MDICNFG_PHY_MASK;
	phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;		phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
	@@ -780,14 +870,14 @@ static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
	{		{
	s32 ret_val;		s32 ret_val;

	ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);		ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
	if (ret_val)		if (ret_val)
	goto out;		goto out;

	ret_val = igb_acquire_nvm(hw);		ret_val = igb_acquire_nvm(hw);

	if (ret_val)		if (ret_val)
	igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);		hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);

	out:		out:
	return ret_val;		return ret_val;
	@@ -803,7 +893,7 @@ static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
	static void igb_release_nvm_82575(struct e1000_hw *hw)		static void igb_release_nvm_82575(struct e1000_hw *hw)
	{		{
	igb_release_nvm(hw);		igb_release_nvm(hw);
	igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);		hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
	}		}

	/**		/**
	@@ -1174,7 +1264,6 @@ static s32 igb_init_hw_82575(struct e1000_hw *hw)
	* is no link.		* is no link.
	*/		*/
	igb_clear_hw_cntrs_82575(hw);		igb_clear_hw_cntrs_82575(hw);

	return ret_val;		return ret_val;
	}		}

	@@ -1211,6 +1300,7 @@ static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
	}		}
	}		}
	switch (hw->phy.type) {		switch (hw->phy.type) {
			case e1000_phy_i210:
	case e1000_phy_m88:		case e1000_phy_m88:
	if (hw->phy.id == I347AT4_E_PHY_ID \|\|		if (hw->phy.id == I347AT4_E_PHY_ID \|\|
	hw->phy.id == M88E1112_E_PHY_ID)		hw->phy.id == M88E1112_E_PHY_ID)
	@@ -1851,7 +1941,7 @@ static s32 igb_reset_hw_82580(struct e1000_hw *hw)

	/* Determine whether or not a global dev reset is requested */		/* Determine whether or not a global dev reset is requested */
	if (global_device_reset &&		if (global_device_reset &&
	igb_acquire_swfw_sync_82575(hw, swmbsw_mask))		hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
	global_device_reset = false;		global_device_reset = false;

	if (global_device_reset &&		if (global_device_reset &&
	@@ -1897,7 +1987,7 @@ static s32 igb_reset_hw_82580(struct e1000_hw *hw)

	/* Release semaphore */		/* Release semaphore */
	if (global_device_reset)		if (global_device_reset)
	igb_release_swfw_sync_82575(hw, swmbsw_mask);		hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);

	return ret_val;		return ret_val;
	}		}

drivers/net/ethernet/intel/igb/e1000_82575.h

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -55,10 +55,11 @@ extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
	#define E1000_SRRCTL_DROP_EN 0x80000000		#define E1000_SRRCTL_DROP_EN 0x80000000
	#define E1000_SRRCTL_TIMESTAMP 0x40000000		#define E1000_SRRCTL_TIMESTAMP 0x40000000


	#define E1000_MRQC_ENABLE_RSS_4Q 0x00000002		#define E1000_MRQC_ENABLE_RSS_4Q 0x00000002
	#define E1000_MRQC_ENABLE_VMDQ 0x00000003		#define E1000_MRQC_ENABLE_VMDQ 0x00000003
	#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
	#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000		#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
			#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
	#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000		#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
	#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000		#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000

drivers/net/ethernet/intel/igb/e1000_defines.h

+33 −0

Original line number	Original line	Diff line number	Diff line
	@@ -458,6 +458,7 @@
	#define E1000_ERR_INVALID_ARGUMENT 16		#define E1000_ERR_INVALID_ARGUMENT 16
	#define E1000_ERR_NO_SPACE 17		#define E1000_ERR_NO_SPACE 17
	#define E1000_ERR_NVM_PBA_SECTION 18		#define E1000_ERR_NVM_PBA_SECTION 18
			#define E1000_ERR_INVM_VALUE_NOT_FOUND 19

	/* Loop limit on how long we wait for auto-negotiation to complete */		/* Loop limit on how long we wait for auto-negotiation to complete */
	#define COPPER_LINK_UP_LIMIT 10		#define COPPER_LINK_UP_LIMIT 10
	@@ -595,6 +596,25 @@
	#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */		#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
	#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */		#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
	#define E1000_EECD_SIZE_EX_SHIFT 11		#define E1000_EECD_SIZE_EX_SHIFT 11
			#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
			#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/
			#define E1000_FLUDONE_ATTEMPTS 20000
			#define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
			#define E1000_I210_FIFO_SEL_RX 0x00
			#define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
			#define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
			#define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
			#define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01
			#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
			#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/
			#define E1000_FLUDONE_ATTEMPTS 20000
			#define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
			#define E1000_I210_FIFO_SEL_RX 0x00
			#define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
			#define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
			#define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
			#define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01


	/* Offset to data in NVM read/write registers */		/* Offset to data in NVM read/write registers */
	#define E1000_NVM_RW_REG_DATA 16		#define E1000_NVM_RW_REG_DATA 16
	@@ -613,6 +633,16 @@
	#define NVM_CHECKSUM_REG 0x003F		#define NVM_CHECKSUM_REG 0x003F
	#define NVM_COMPATIBILITY_REG_3 0x0003		#define NVM_COMPATIBILITY_REG_3 0x0003
	#define NVM_COMPATIBILITY_BIT_MASK 0x8000		#define NVM_COMPATIBILITY_BIT_MASK 0x8000
			#define NVM_MAC_ADDR 0x0000
			#define NVM_SUB_DEV_ID 0x000B
			#define NVM_SUB_VEN_ID 0x000C
			#define NVM_DEV_ID 0x000D
			#define NVM_VEN_ID 0x000E
			#define NVM_INIT_CTRL_2 0x000F
			#define NVM_INIT_CTRL_4 0x0013
			#define NVM_LED_1_CFG 0x001C
			#define NVM_LED_0_2_CFG 0x001F


	#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */		#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
	#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */		#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
	@@ -639,6 +669,7 @@

	#define NVM_PBA_OFFSET_0 8		#define NVM_PBA_OFFSET_0 8
	#define NVM_PBA_OFFSET_1 9		#define NVM_PBA_OFFSET_1 9
			#define NVM_RESERVED_WORD 0xFFFF
	#define NVM_PBA_PTR_GUARD 0xFAFA		#define NVM_PBA_PTR_GUARD 0xFAFA
	#define NVM_WORD_SIZE_BASE_SHIFT 6		#define NVM_WORD_SIZE_BASE_SHIFT 6

	@@ -696,6 +727,7 @@
	#define I82580_I_PHY_ID 0x015403A0		#define I82580_I_PHY_ID 0x015403A0
	#define I350_I_PHY_ID 0x015403B0		#define I350_I_PHY_ID 0x015403B0
	#define M88_VENDOR 0x0141		#define M88_VENDOR 0x0141
			#define I210_I_PHY_ID 0x01410C00

	/* M88E1000 Specific Registers */		/* M88E1000 Specific Registers */
	#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */		#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
	@@ -815,6 +847,7 @@
	#define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* EEE Enable 100M AN */		#define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* EEE Enable 100M AN */
	#define E1000_EEER_TX_LPI_EN 0x00010000 /* EEE Tx LPI Enable */		#define E1000_EEER_TX_LPI_EN 0x00010000 /* EEE Tx LPI Enable */
	#define E1000_EEER_RX_LPI_EN 0x00020000 /* EEE Rx LPI Enable */		#define E1000_EEER_RX_LPI_EN 0x00020000 /* EEE Rx LPI Enable */
			#define E1000_EEER_FRC_AN 0x10000000 /* Enable EEE in loopback */
	#define E1000_EEER_LPI_FC 0x00040000 /* EEE Enable on FC */		#define E1000_EEER_LPI_FC 0x00040000 /* EEE Enable on FC */

	/* SerDes Control */		/* SerDes Control */

drivers/net/ethernet/intel/igb/e1000_hw.h

+14 −0

Original line number	Original line	Diff line number	Diff line
	@@ -63,6 +63,13 @@ struct e1000_hw;
	#define E1000_DEV_ID_I350_FIBER 0x1522		#define E1000_DEV_ID_I350_FIBER 0x1522
	#define E1000_DEV_ID_I350_SERDES 0x1523		#define E1000_DEV_ID_I350_SERDES 0x1523
	#define E1000_DEV_ID_I350_SGMII 0x1524		#define E1000_DEV_ID_I350_SGMII 0x1524
			#define E1000_DEV_ID_I210_COPPER 0x1533
			#define E1000_DEV_ID_I210_COPPER_OEM1 0x1534
			#define E1000_DEV_ID_I210_COPPER_IT 0x1535
			#define E1000_DEV_ID_I210_FIBER 0x1536
			#define E1000_DEV_ID_I210_SERDES 0x1537
			#define E1000_DEV_ID_I210_SGMII 0x1538
			#define E1000_DEV_ID_I211_COPPER 0x1539

	#define E1000_REVISION_2 2		#define E1000_REVISION_2 2
	#define E1000_REVISION_4 4		#define E1000_REVISION_4 4
	@@ -83,6 +90,8 @@ enum e1000_mac_type {
	e1000_82576,		e1000_82576,
	e1000_82580,		e1000_82580,
	e1000_i350,		e1000_i350,
			e1000_i210,
			e1000_i211,
	e1000_num_macs /* List is 1-based, so subtract 1 for true count. */		e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
	};		};

	@@ -117,6 +126,7 @@ enum e1000_phy_type {
	e1000_phy_igp_3,		e1000_phy_igp_3,
	e1000_phy_ife,		e1000_phy_ife,
	e1000_phy_82580,		e1000_phy_82580,
			e1000_phy_i210,
	};		};

	enum e1000_bus_type {		enum e1000_bus_type {
	@@ -313,6 +323,9 @@ struct e1000_mac_operations {
	void (rar_set)(struct e1000_hw , u8 *, u32);		void (rar_set)(struct e1000_hw , u8 *, u32);
	s32 (read_mac_addr)(struct e1000_hw );		s32 (read_mac_addr)(struct e1000_hw );
	s32 (get_speed_and_duplex)(struct e1000_hw , u16 , u16 );		s32 (get_speed_and_duplex)(struct e1000_hw , u16 , u16 );
			s32 (acquire_swfw_sync)(struct e1000_hw , u16);
			void (release_swfw_sync)(struct e1000_hw , u16);

	};		};

	struct e1000_phy_operations {		struct e1000_phy_operations {
	@@ -338,6 +351,7 @@ struct e1000_nvm_operations {
	s32 (write)(struct e1000_hw , u16, u16, u16 *);		s32 (write)(struct e1000_hw , u16, u16, u16 *);
	s32 (update)(struct e1000_hw );		s32 (update)(struct e1000_hw );
	s32 (validate)(struct e1000_hw );		s32 (validate)(struct e1000_hw );
			s32 (valid_led_default)(struct e1000_hw , u16 *);
	};		};

	struct e1000_info {		struct e1000_info {