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Commit f7e27e8b authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

ARM: dts: msm: Add dummy NPU clocks support on SDM855 



Add the clock device tree node for npucc. Also add the header file
with all the clock references for clients to use.

Change-Id: I293465e1f785c2f920a1beb922a2ce5389a2eb42
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent d7b25266

arch/arm64/boot/dts/qcom/sdm855.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include <dt-bindings/clock/qcom,gpucc-sdm855.h>

#include <dt-bindings/clock/qcom,videocc-sdm855.h>

#include <dt-bindings/clock/qcom,cpucc-sdm855.h>

#include <dt-bindings/clock/qcom,npucc-sdm855.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/clock/qcom,aop-qmp.h>
@@ -464,6 +465,13 @@ 
		#reset-cells = <1>;

	};



	clock_npucc: qcom,npucc {

		compatible = "qcom,dummycc";

		clock-output-names = "npucc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_gpucc: qcom,dispcc {

		compatible = "qcom,dummycc";

		clock-output-names = "gpucc_clocks";

include/dt-bindings/clock/qcom,npucc-sdm855.h

0 → 100644
+44 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_NPU_CC_SDM855_H

#define _DT_BINDINGS_CLK_QCOM_NPU_CC_SDM855_H



#define NPU_CC_ARMWIC_CORE_CLK					0

#define NPU_CC_BTO_CORE_CLK					1

#define NPU_CC_BWMON_CLK					2

#define NPU_CC_CAL_DP_CDC_CLK					3

#define NPU_CC_CAL_DP_CLK					4

#define NPU_CC_CAL_DP_CLK_SRC					5

#define NPU_CC_COMP_NOC_AXI_CLK					6

#define NPU_CC_CONF_NOC_AHB_CLK					7

#define NPU_CC_NPU_CORE_APB_CLK					8

#define NPU_CC_NPU_CORE_ATB_CLK					9

#define NPU_CC_NPU_CORE_CLK					10

#define NPU_CC_NPU_CORE_CLK_SRC					11

#define NPU_CC_NPU_CORE_CTI_CLK					12

#define NPU_CC_NPU_CPC_CLK					13

#define NPU_CC_NPU_CPC_TIMER_CLK				14

#define NPU_CC_PERF_CNT_CLK					15

#define NPU_CC_PLL0						16

#define NPU_CC_PLL0_OUT_EVEN					17

#define NPU_CC_PLL1						18

#define NPU_CC_PLL1_OUT_EVEN					19

#define NPU_CC_QTIMER_CORE_CLK					20

#define NPU_CC_SLEEP_CLK					21

#define NPU_CC_XO_CLK						22



#define NPU_CC_CAL_DP_BCR					0

#define NPU_CC_NPU_CORE_BCR					1



#endif