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Commit f7a46fa7 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
Browse files

MIPS: save/restore MSACSR register on context switch 



I added a field for the MSACSR register in struct mips_fpu_struct, but
never actually made use of it... This is a clear bug. Save and restore
the MSACSR register along with the vector registers.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7300/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 558155a0

arch/mips/include/asm/asmmacro.h

+11 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 


#include <asm/hazards.h>

#include <asm/asm-offsets.h>

#include <asm/msa.h>



#ifdef CONFIG_32BIT

#include <asm/asmmacro-32.h>
@@ -378,9 +379,19 @@ 
	st_d	29, THREAD_FPR29, \thread

	st_d	30, THREAD_FPR30, \thread

	st_d	31, THREAD_FPR31, \thread

	.set	push

	.set	noat

	cfcmsa	$1, MSA_CSR

	sw	$1, THREAD_MSA_CSR(\thread)

	.set	pop

	.endm



	.macro	msa_restore_all	thread

	.set	push

	.set	noat

	lw	$1, THREAD_MSA_CSR(\thread)

	ctcmsa	MSA_CSR, $1

	.set	pop

	ld_d	0, THREAD_FPR0, \thread

	ld_d	1, THREAD_FPR1, \thread

	ld_d	2, THREAD_FPR2, \thread

arch/mips/kernel/asm-offsets.c

+1 −0
Original line number Diff line number Diff line
@@ -234,6 +234,7 @@ void output_thread_fpu_defines(void) 
	       thread.fpu.fpr[31].val64[FPR_IDX(64, 0)]);



	OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);

	OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr);

	BLANK();

}