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Commit f7449a8c authored by Narender Ankam's avatar Narender Ankam
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clk: qcom: mdss: use correct HDMI PLL divider 



HDMI PLL divider divsel_six is preferred over divsel_four
to keep vco range within goal limits to maintain margin.
To achieve this, its precedence order is toggled at mux
level. So reverse toggle the mux_sel value during mux
selection.

Change-Id: I90d98e061978109d65136bbd77641d6cfff9f61a
Signed-off-by: default avatarNarender Ankam <nankam@codeaurora.org>
parent 72af9a4d

drivers/clk/qcom/mdss/mdss-hdmi-pll-28lpm.c

+17 −0
Original line number Diff line number Diff line
@@ -539,6 +539,8 @@ static int hdmi_mux_set_parent(void *context, unsigned int reg, 
	struct mdss_pll_resources *hdmi_pll_res = context;

	int rc = 0;

	u32 reg_val = 0;

	const u32 div_4 = 0x20;

	const u32 div_6 = 0x30;



	rc = mdss_pll_resource_enable(hdmi_pll_res, true);

	if (rc) {
@@ -546,6 +548,21 @@ static int hdmi_mux_set_parent(void *context, unsigned int reg, 
		return rc;

	}



	/*

	 * divsel_six is preferred over divsel_four to keep

	 * vco range within goal limits to maintain margin.

	 * To achieve this, its precedence order is toggled

	 * at mux level. So reverse toggle the mux_sel value

	 * here.

	 */

	switch (mux_sel) {

	case 0x20: /* intended divider is divsel_six */

		mux_sel = div_6;

		break;

	case 0x30: /* intended divider is divsel_four */

		mux_sel = div_4;

		break;

	}

	pr_debug("mux_sel = %d\n", mux_sel);



	reg_val = MDSS_PLL_REG_R(hdmi_pll_res->pll_base,