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Commit f6e194a1 authored by Jayant Shekhar's avatar Jayant Shekhar
Browse files

drm/msm/sde: Add support for selecting LM for CWB 



There is no requirement populated for CWB pinpong, it
chooses in first come first serve basis. But there can
be MDSS revision HW which allows only specific pingpong
for CWB. Add support for same to reserve correct LM
for CWB path.

Change-Id: I0f7cd01671112529f069332014072f272245129d
Signed-off-by: default avatarJayant Shekhar <jshekhar@codeaurora.org>
parent b278d157

Documentation/devicetree/bindings/display/msm/sde.txt

+6 −0
Original line number Diff line number Diff line
@@ -424,6 +424,10 @@ Optional properties: 
				for the mixer block. Possible values:

				"primary" - preferred for primary display

				"none" - no preference on display

- qcom,sde-mixer-cwb-pref:  	A string array indicating the preferred mixer block.

				for CWB. Possible values:

				"cwb" - preferred for cwb

				"none" - no preference on display

- qcom,sde-ctl-display-pref:    A string array indicating the preferred display type

                                for the ctl block. Possible values:

				"primary" - preferred for primary display
@@ -523,6 +527,8 @@ Example: 
			0x00047000 0x0004a000>;

    qcom,sde-mixer-display-pref = "primary", "none",

	                "none", "none";

    qcom,sde-mixer-cwb-pref = "none", "none",

	                "cwb", "none";

    qcom,sde-dspp-top-off = <0x1300>;

    qcom,sde-dspp-off = <0x00055000 0x00057000>;

    qcom,sde-dspp-ad-off = <0x24000 0x22800>;

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+9 −0
Original line number Diff line number Diff line
@@ -333,6 +333,7 @@ enum { 
	MIXER_PAIR_MASK,

	MIXER_BLOCKS,

	MIXER_DISP,

	MIXER_CWB,

	MIXER_PROP_MAX,

};
@@ -571,6 +572,8 @@ static struct sde_prop_type mixer_prop[] = { 
	{MIXER_BLOCKS, "qcom,sde-mixer-blocks", false, PROP_TYPE_NODE},

	{MIXER_DISP, "qcom,sde-mixer-display-pref", false,

		PROP_TYPE_STRING_ARRAY},

	{MIXER_CWB, "qcom,sde-mixer-cwb-pref", false,

		PROP_TYPE_STRING_ARRAY},

};



static struct sde_prop_type mixer_blocks_prop[] = {
@@ -1626,6 +1629,7 @@ static int sde_mixer_parse_dt(struct device_node *np, 
	for (i = 0, mixer_count = 0, pp_idx = 0, dspp_idx = 0,

			ds_idx = 0; i < off_count; i++) {

		const char *disp_pref = NULL;

		const char *cwb_pref = NULL;



		mixer_base = PROP_VALUE_ACCESS(prop_value, MIXER_OFF, i);

		if (!mixer_base)
@@ -1673,6 +1677,11 @@ static int sde_mixer_parse_dt(struct device_node *np, 
		if (disp_pref && !strcmp(disp_pref, "primary"))

			set_bit(SDE_DISP_PRIMARY_PREF, &mixer->features);



		of_property_read_string_index(np,

			mixer_prop[MIXER_CWB].prop_name, i, &cwb_pref);

		if (cwb_pref && !strcmp(cwb_pref, "cwb"))

			set_bit(SDE_DISP_CWB_PREF, &mixer->features);



		mixer->pingpong = pp_count > 0 ? pp_idx + PINGPONG_0

							: PINGPONG_MAX;

		mixer->dspp = dspp_count > 0 ? dspp_idx + DSPP_0

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+2 −0
Original line number Diff line number Diff line
@@ -203,6 +203,7 @@ enum { 
 * @SDE_MIXER_SOURCESPLIT     Layer mixer supports source-split configuration

 * @SDE_MIXER_GC              Gamma correction block

 * @SDE_DIM_LAYER             Layer mixer supports dim layer

 * @SDE_DISP_CWB_PREF         Layer mixer preferred for CWB

 * @SDE_DISP_PRIMARY_PREF     Layer mixer preferred for primary display

 * @SDE_MIXER_MAX             maximum value

 */
@@ -212,6 +213,7 @@ enum { 
	SDE_MIXER_GC,

	SDE_DIM_LAYER,

	SDE_DISP_PRIMARY_PREF,

	SDE_DISP_CWB_PREF,

	SDE_MIXER_MAX

};

drivers/gpu/drm/msm/sde/sde_rm.c

+22 −3
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ 
#define RM_RQ_CLEAR(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_CLEAR))

#define RM_RQ_DSPP(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DSPP))

#define RM_RQ_DS(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DS))

#define RM_RQ_CWB(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_CWB))

#define RM_IS_TOPOLOGY_MATCH(t, r) ((t).num_lm == (r).num_lm && \

				(t).num_comp_enc == (r).num_enc && \

				(t).num_intf == (r).num_intf)
@@ -610,16 +611,17 @@ static bool _sde_rm_check_lm_and_get_connected_blks( 
	const struct sde_pingpong_cfg *pp_cfg;

	struct sde_rm_hw_iter iter;

	bool is_valid_dspp, is_valid_ds, ret;

	u32 display_pref;

	u32 display_pref, cwb_pref;



	*dspp = NULL;

	*ds = NULL;

	*pp = NULL;

	display_pref = lm_cfg->features & BIT(SDE_DISP_PRIMARY_PREF);

	cwb_pref = lm_cfg->features & BIT(SDE_DISP_CWB_PREF);



	SDE_DEBUG("check lm %d: dspp %d ds %d pp %d display_pref: %d\n",

	SDE_DEBUG("check lm %d: dspp %d ds %d pp %d disp_pref: %d cwb_pref%d\n",

		lm_cfg->id, lm_cfg->dspp, lm_cfg->ds,

		lm_cfg->pingpong, display_pref);

		lm_cfg->pingpong, display_pref, cwb_pref);



	/* Check if this layer mixer is a peer of the proposed primary LM */

	if (primary_lm) {
@@ -661,6 +663,16 @@ static bool _sde_rm_check_lm_and_get_connected_blks( 
				lm_cfg->ds);

			return ret;

		}



		/**

		 * If CWB is enabled and LM is not CWB supported

		 * then return false.

		 */

		if (RM_RQ_CWB(reqs) && !cwb_pref) {

			SDE_DEBUG("fail: cwb supported lm not allocated\n");

			return false;

		}



	} else if (!(reqs->hw_res.is_primary && display_pref)) {

		SDE_DEBUG(

			"display preference is not met. is_primary: %d display_pref: %d\n",
@@ -1737,6 +1749,13 @@ static int _sde_rm_populate_requirements( 
		conn_state->connector->connector_type == DRM_MODE_CONNECTOR_DSI)

		reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DS);



	/**

	 * Set the requirement for LM which has CWB support if CWB is

	 * found enabled.

	 */

	if (!RM_RQ_CWB(reqs) && sde_encoder_in_clone_mode(enc))

		reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_CWB);



	SDE_DEBUG("top_ctrl: 0x%llX num_h_tiles: %d\n", reqs->top_ctrl,

			reqs->hw_res.display_num_of_h_tiles);

	SDE_DEBUG("num_lm: %d num_ctl: %d topology: %d split_display: %d\n",

drivers/gpu/drm/msm/sde/sde_rm.h

+2 −0
Original line number Diff line number Diff line
@@ -57,12 +57,14 @@ enum sde_rm_topology_name { 
 *                               reservation list during the AtomicTest phase.

 * @SDE_RM_TOPCTL_DSPP: Require layer mixers with DSPP capabilities

 * @SDE_RM_TOPCTL_DS  : Require layer mixers with DS capabilities

 * @SDE_RM_TOPCTL_CWB  : Require layer mixers with CWB capabilities

 */

enum sde_rm_topology_control {

	SDE_RM_TOPCTL_RESERVE_LOCK,

	SDE_RM_TOPCTL_RESERVE_CLEAR,

	SDE_RM_TOPCTL_DSPP,

	SDE_RM_TOPCTL_DS,

	SDE_RM_TOPCTL_CWB,

};



/**