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Commit f6a09bac authored by Eugeniy Paltsev's avatar Eugeniy Paltsev Committed by Vineet Gupta
Browse files

ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk 



Add core pll node (core_clk) to manage cpu frequency.
core_clk represents pll itself.
input_clk represents clock signal source (basically xtal) which
comes to pll input.

Signed-off-by: default avatarEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent 9926c29f

arch/arc/boot/dts/axc003.dtsi

+9 −2
Original line number Original line Diff line number Diff line
@@ -24,10 +24,17 @@ 




		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;

		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;





		core_clk: core_clk {

		input_clk: input-clk {

			#clock-cells = <0>;

			#clock-cells = <0>;

			compatible = "fixed-clock";

			compatible = "fixed-clock";

			clock-frequency = <90000000>;

			clock-frequency = <33333333>;

		};



		core_clk: core-clk@80 {

			compatible = "snps,axs10x-arc-pll-clock";

			reg = <0x80 0x10>, <0x100 0x10>;

			#clock-cells = <0>;

			clocks = <&input_clk>;

		};

		};





		core_intc: archs-intc@cpu {

		core_intc: archs-intc@cpu {

arch/arc/boot/dts/axc003_idu.dtsi

+9 −2
Original line number Original line Diff line number Diff line
@@ -24,10 +24,17 @@ 




		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;

		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;





		core_clk: core_clk {

		input_clk: input-clk {

			#clock-cells = <0>;

			#clock-cells = <0>;

			compatible = "fixed-clock";

			compatible = "fixed-clock";

			clock-frequency = <100000000>;

			clock-frequency = <33333333>;

		};



		core_clk: core-clk@80 {

			compatible = "snps,axs10x-arc-pll-clock";

			reg = <0x80 0x10>, <0x100 0x10>;

			#clock-cells = <0>;

			clocks = <&input_clk>;

		};

		};





		core_intc: archs-intc@cpu {

		core_intc: archs-intc@cpu {