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Commit f67565c3 authored by Marc Zyngier's avatar Marc Zyngier Committed by Gerrit - the friendly Code Review server
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arm64: arch_timer: Add workaround for ARM erratum 1188873 



When running on Cortex-A76, a timer access from an AArch32 EL0
task may end up with a corrupted value or register. The workaround for
this is to trap these accesses at EL1/EL2 and execute them there.

This only affects versions r0p0, r1p0 and r2p0 of the CPU.

Change-Id: If2026eff975725d41dc2f1630ab086f3cc7deea3
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Git-commit: 95b861a4a6d94f64d5242605569218160ebacdbe
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git


[neeraju@codeaurora: Resolve trivial merge conflicts.]
Signed-off-by: default avatarNeeraj Upadhyay <neeraju@codeaurora.org>
[sramana@codeaurora: Resolve trivial merge conflicts.]
Signed-off-by: default avatarSrinivas Ramana <sramana@codeaurora.org>
parent 29444f60

arch/arm64/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -522,6 +522,16 @@ config ARM64_ERRATUM_1286807 
	  invalidated has been observed by other observers. The

	  workaround repeats the TLBI+DSB operation.



config ARM64_ERRATUM_1188873

	bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"

	default y

	help

	  This option adds work arounds for ARM Cortex-A76 erratum 1188873



	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause

	  register corruption when accessing the timer registers from

	  AArch32 userspace.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -47,7 +47,8 @@ 
#define ARM64_SSBD				27

#define ARM64_MISMATCHED_CACHE_TYPE		28

#define ARM64_SSBS				29

#define ARM64_WORKAROUND_1188873		30



#define ARM64_NCAPS				30

#define ARM64_NCAPS				31



#endif /* __ASM_CPUCAPS_H */

arch/arm64/kernel/cpu_errata.c

+10 −0
Original line number Diff line number Diff line
@@ -644,6 +644,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.capability = ARM64_SSBD,

		.matches = has_ssbd_mitigation,

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1188873

	{

		/* Cortex-A76 r0p0 to r2p0 */

		.desc = "ARM erratum 1188873",

		.capability = ARM64_WORKAROUND_1188873,

		MIDR_RANGE(MIDR_CORTEX_A76,

			MIDR_CPU_VAR_REV(0, 0),

			MIDR_CPU_VAR_REV(2, 0)),

	},

#endif

	{

	}

drivers/clocksource/arm_arch_timer.c

+15 −0
Original line number Diff line number Diff line
@@ -301,6 +301,13 @@ static u64 notrace arm64_858921_read_cntvct_el0(void) 
}

#endif



#ifdef CONFIG_ARM64_ERRATUM_1188873

static u64 notrace arm64_1188873_read_cntvct_el0(void)

{

	return read_sysreg(cntvct_el0);

}

#endif



#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND

DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *,

	       timer_unstable_counter_workaround);
@@ -384,6 +391,14 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { 
		.read_cntvct_el0 = arm64_858921_read_cntvct_el0,

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1188873

	{

		.match_type = ate_match_local_cap_id,

		.id = (void *)ARM64_WORKAROUND_1188873,

		.desc = "ARM erratum 1188873",

		.read_cntvct_el0 = arm64_1188873_read_cntvct_el0,

	},

#endif

};



typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,