Loading drivers/clk/qcom/dispcc-sdmmagpie.c +4 −3 Original line number Diff line number Diff line Loading @@ -104,7 +104,7 @@ static const struct parent_map disp_cc_parent_map_3[] = { static const char * const disp_cc_parent_names_3[] = { "bi_tcxo", "disp_cc_pll0", "gpll0", "gcc_disp_gpll0_clk_src", "disp_cc_pll0_out_even", "core_bi_pll_test_se", }; Loading @@ -131,7 +131,7 @@ static const struct parent_map disp_cc_parent_map_5[] = { static const char * const disp_cc_parent_names_5[] = { "bi_tcxo", "gpll0", "gcc_disp_gpll0_clk_src", "core_bi_pll_test_se", }; Loading Loading @@ -195,6 +195,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { .name = "disp_cc_mdss_ahb_clk_src", .parent_names = disp_cc_parent_names_5, .num_parents = 3, .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, Loading Loading @@ -636,7 +637,7 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = { "disp_cc_mdss_byte0_div_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, .flags = CLK_GET_RATE_NOCACHE, .ops = &clk_branch2_ops, }, }, Loading drivers/clk/qcom/gpucc-sdmmagpie.c +2 −2 Original line number Diff line number Diff line Loading @@ -312,7 +312,7 @@ static struct clk_branch gpu_cc_acd_cxo_clk = { static struct clk_branch gpu_cc_ahb_clk = { .halt_reg = 0x1078, .halt_check = BRANCH_HALT, .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x1078, .enable_mask = BIT(0), Loading Loading @@ -458,7 +458,7 @@ static struct clk_branch gpu_cc_gx_cxo_clk = { static struct clk_branch gpu_cc_gx_gfx3d_clk = { .halt_reg = 0x1054, .halt_check = BRANCH_HALT, .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x1054, .enable_mask = BIT(0), Loading Loading
drivers/clk/qcom/dispcc-sdmmagpie.c +4 −3 Original line number Diff line number Diff line Loading @@ -104,7 +104,7 @@ static const struct parent_map disp_cc_parent_map_3[] = { static const char * const disp_cc_parent_names_3[] = { "bi_tcxo", "disp_cc_pll0", "gpll0", "gcc_disp_gpll0_clk_src", "disp_cc_pll0_out_even", "core_bi_pll_test_se", }; Loading @@ -131,7 +131,7 @@ static const struct parent_map disp_cc_parent_map_5[] = { static const char * const disp_cc_parent_names_5[] = { "bi_tcxo", "gpll0", "gcc_disp_gpll0_clk_src", "core_bi_pll_test_se", }; Loading Loading @@ -195,6 +195,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { .name = "disp_cc_mdss_ahb_clk_src", .parent_names = disp_cc_parent_names_5, .num_parents = 3, .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, Loading Loading @@ -636,7 +637,7 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = { "disp_cc_mdss_byte0_div_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, .flags = CLK_GET_RATE_NOCACHE, .ops = &clk_branch2_ops, }, }, Loading
drivers/clk/qcom/gpucc-sdmmagpie.c +2 −2 Original line number Diff line number Diff line Loading @@ -312,7 +312,7 @@ static struct clk_branch gpu_cc_acd_cxo_clk = { static struct clk_branch gpu_cc_ahb_clk = { .halt_reg = 0x1078, .halt_check = BRANCH_HALT, .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x1078, .enable_mask = BIT(0), Loading Loading @@ -458,7 +458,7 @@ static struct clk_branch gpu_cc_gx_cxo_clk = { static struct clk_branch gpu_cc_gx_gfx3d_clk = { .halt_reg = 0x1054, .halt_check = BRANCH_HALT, .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x1054, .enable_mask = BIT(0), Loading